restructure media

modules/module_0_foundations/README.md

@@ -1,10 +0,0 @@
-### Lookup Table Generation
-
-To generate the lookup tables (LUTs) used in this chapter, we utilized resources from the GitHub repository by [medwatt](https://github.com/medwatt). Specifically, the LUT generation was based on his excellent [`gmid`](https://github.com/medwatt/gmid) project, which provides detailed documentation and well-structured scripts for generating lookup tables. Many thanks to medwatt for making this resource available — if you're working on similar tasks, I highly recommend taking a look at the repository!
-
-The scripts that was made for generating the LUTs can be found as:
-
-- `sg13_nmos_lv.py`
-- `sg13_pmos_lv.py`
-
-For a practical use case and a more detailed explanation of how these LUTs are applied, please refer to the slides (Introduction_and_welcome_1)

modules/module_0_foundations/foundations.md

@@ -19,7 +19,7 @@ After following the installation steps, you should be able to launch Xschem by e
     xschem
 
 Upon launching, the initial Xschem window should appear as follows:
-<p align="center"> <img src="../../media/module_0/main_menu.png" width="800" height="400" /> </p>
+<p align="center"> <img src=".media/main_menu.png" width="800" height="400" /> </p>
 
 This view includes test cases within the IHP PDK, demonstrating different types of simulations. Below is an overview of each type:
 
@@ -32,7 +32,7 @@ This view includes test cases within the IHP PDK, demonstrating different types
 The simulation library allows you to explore different designs and understand the simulation setups, which will be covered in detail throughout the course. To get started, try opening dc_lv_nmos by selecting the instance and pressing e. This will open the schematic view.
 
 From here, navigate to the "netlist" button in the top-right corner, then press "simulate." Your first schematic simulation in Xschem will now be complete. View the results by left-clicking the green arrow while holding down Ctrl. The output should look like this:
-<p align="center"> <img src="../../media/module_0/dc_sim.png" width="800" height="400" /> </p>
+<p align="center"> <img src=".media/dc_sim.png" width="800" height="400" /> </p>
 
 If the dark mode theme is hard to read, you can toggle it by pressing "Shift + O."
 

modules/module_0_foundations/scripting/gmid_test.ipynb

@@ -2,7 +2,7 @@
  "cells": [
   {
    "cell_type": "code",
-   "execution_count": 101,
+   "execution_count": 1,
    "id": "9f325daf-eb3b-4cf7-8ffe-b9b94e7f66ea",
    "metadata": {},
    "outputs": [],
@@ -18,7 +18,7 @@
   },
   {
    "cell_type": "code",
-   "execution_count": 102,
+   "execution_count": 2,
    "id": "b5b31aca-47bf-4461-8e50-16c20f03b337",
    "metadata": {},
    "outputs": [],
@@ -29,7 +29,7 @@
   },
   {
    "cell_type": "code",
-   "execution_count": 103,
+   "execution_count": 4,
    "id": "a03cd944-2432-457c-9b88-486ab781fde6",
    "metadata": {},
    "outputs": [
@@ -37,17 +37,17 @@
      "name": "stdout",
      "output_type": "stream",
      "text": [
-      "dict_keys(['sg13_lv_nmos ', 'sg13_lv_pmos', 'description', 'simulator', 'parameter_names', 'device_parameters'])\n"
+      "dict_keys(['sg13_lv_nmos ', 'description', 'simulator', 'parameter_names', 'device_parameters'])\n"
      ]
     }
    ],
    "source": [
-    "print(lookup_table.keys())"
+    "print(lookup_table_nmos.keys())"
    ]
   },
   {
    "cell_type": "code",
-   "execution_count": 108,
+   "execution_count": 5,
    "id": "743dc381-0d35-4aa9-847c-c42c80c17786",
    "metadata": {},
    "outputs": [],
@@ -63,7 +63,7 @@
   },
   {
    "cell_type": "code",
-   "execution_count": 109,
+   "execution_count": 6,
    "id": "b27d5fca-3436-4df7-895f-f6a4bbd7a80d",
    "metadata": {
     "jupyter": {
@@ -257,14 +257,14 @@
   },
   {
    "cell_type": "code",
-   "execution_count": 110,
+   "execution_count": 7,
    "id": "b7cc630f-b385-47a6-a6f9-ac0d10effffe",
    "metadata": {},
    "outputs": [
     {
      "data": {
       "application/vnd.jupyter.widget-view+json": {
-       "model_id": "f4bd29dd4a254e499496ceb2f8444c8f",
+       "model_id": "b5ed71dbc38a4a55b7b1717f2b0ca7d2",
        "version_major": 2,
        "version_minor": 0
       },

modules/module_1_bandgap_reference/Introduction.md

@@ -12,7 +12,7 @@ $$V_{BE} = V_T \cdot ln(\frac{I_C}{I_S})$$
 Where $I_C$ is the collector current and $I_S$ is the saturation current. 
 The theory behind different circuit topology regarding the bandgap references are quite comprehensive, and will therefore not be covered here. Instead the circuit seen below is proposed:
 
-<p align="center"> <img src="../../media/module_1/bandgap_circuit.png" width="800" height="700" /> </p>
+<p align="center"> <img src=".media/bandgap_circuit.png" width="800" height="700" /> </p>
 
 
 From the following criteria, $I_{C,Q1}=I_{C,Q2}$ if $R_2 = R_3$, we can try to understand the circuit functionality. The voltage X and Y is forced to be equal due to the operation of the feedback of the OP-amps. This means that we can write the following expression

modules/module_1_bandgap_reference/part_1_OTA/design_of_ota.md

@@ -9,7 +9,7 @@ The first step in the procedure is to create the schematic for the two-stage OTA
 Step 2: Instantiating Transistors
 
 Next, instantiate six MOSFETs (three PMOS and two NMOS) using the IHP Open PDK. Refer to the foundation markdown file from Module 0 for guidance on adding these components. Arrange the transistors as illustrated below, configuring their parameters accordingly:
-<p align="center"> <img src="../../../media/module_1/OTA_images/first_stage_img.png" width="1000" height="700" /> </p>
+<p align="center"> <img src=".media/first_stage_img.png" width="1000" height="700" /> </p>
 
 To locate the required labels, open the Components Manager and search for iopin.sym under xschem_library/devices.
 
@@ -28,7 +28,7 @@ First step in our procedure is to create the schematic for the OTA we will use i
 Next, instantiate six MOSFETs (three PMOS and two NMOS) from the IHP Open PDK. Refer to the foundations markdown file from Module 0 for guidance on adding these components. Arrange the transistors as shown in the image below and configure their parameters accordingly.
 
 <p align="center">
-  <img src="../../../media/module_1/OTA_images/first_stage_img.png" width="1000" height="700" />
+  <img src=".media/first_stage_img.png" width="1000" height="700" />
 </p>
 
 To locate the necessary labels, open the Components Manager and search for `iopin.sym` under `xschem_library/devices`.
@@ -47,7 +47,7 @@ For clarity, here are the transistor dimensions for the initial stage:
 
 Proceed to draw the output stage, which includes a Miller compensation capacitor. Follow the configuration shown below:
 
-<p align="center"> <img src="../../../media/module_1/OTA_images/full_system_img.png" width="1000" height="600" /> </p>
+<p align="center"> <img src=".media/full_system_img.png" width="1000" height="600" /> </p>
 
 
 Dimensions for the output stage components are as follows:
@@ -79,7 +79,7 @@ Its also possible to remove the bias current pin and replace with an actual on c
 
 In symbol mode, Xschem automatically creates a small rectangle that includes pins with default names based on your schematic. Give the symbol an appropriate name and you should see the following
 
-<p align="center"> <img src="../../../media/module_1/OTA_images/symbol_1.png" width="500" height="400" /> </p>
+<p align="center"> <img src=".media/symbol_1.png" width="500" height="400" /> </p>
 
 
 ### Step 4: Designing the Symbol Shape
@@ -89,7 +89,7 @@ Now, using the **Draw** tools in Xschem, modify the default rectangle to create
 If you’re interested in learning to create more complex shapes, there are resources on YouTube and other platforms. However, if you already have experience drawing schematic symbols, this step should feel straightforward. Refer to the provided images as a guide for arranging the shape and positioning the pins for a clean, organized symbol.
 
 
-<p align="center"> <img src="../../../media/module_1/OTA_images/ota_sym.png" width="500" height="400" /> </p>
+<p align="center"> <img src=".media/ota_sym.png" width="500" height="400" /> </p>
 
 
 (Note: If the grid size and snapping values are too big, you can adjust at view - -> Set snap value/set grid spacing )
@@ -145,7 +145,7 @@ To set up the first testbench for simulating the open-loop frequency response of
 5. **Verify the Setup**:
     
     - At this point, your schematic should resemble the provided image, ensuring all components are placed and connected correctly.
-    <p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_1.png" width="1000" height="700" /> </p>
+    <p align="center"> <img src=".media/tb_img_1.png" width="1000" height="700" /> </p>
 As you may see there is additional components in the picture. The reasoning behind this can be seen in the following sections
 #### **Series Feedback with Infinite Inductor**
 
@@ -205,7 +205,7 @@ In the **Value** field, insert the following code:
     - **`mos_tt`**: Specifies the **Typical-Typical (TT)** process corner for the MOSFETs
 
 By including this code block, you ensure the simulation has access to the correct models and process corners. At this point, your code block should resemble the provided image.
-<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_3.png" width="450" height="300" /> </p>
+<p align="center"> <img src=".media/tb_img_3.png" width="450" height="300" /> </p>
 
 ### Extra Information About process corners: Understanding Variations in Semiconductor Fabrication
 Process corners are sets of predefined conditions that account for variations in semiconductor manufacturing processes. These variations affect the electrical characteristics of devices (like MOSFETs and capacitors) and can impact circuit performance. Simulating across process corners ensures your design works reliably under real-world manufacturing tolerances.
@@ -300,7 +300,7 @@ write output_file.raw
 - **`write output_file.raw`**: Saves the AC analysis results to a raw file for further processing.
 #### **Verifying the Code Block**
 The complete code block should look as shown in the image below:
-<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_4.png" width="250" height="250" /> </p>
+<p align="center"> <img src=".media/tb_img_4.png" width="250" height="250" /> </p>
 
 
 ### Step 6: Running simulation and confirming operation
@@ -341,7 +341,7 @@ tclcommand="xschem raw_read $netlist_dir/output_file.raw ac"
 ```
 After this press ctrl and left click the arrow, and after this double click the bottom plot. From here you should see all the avaliable signals for plotting and select the ph(vout). This gives the phase response. This is used instead of the statement we defined since xschem automatically saves the data in the raw format as a complex number with a real and imaginary number. From check the Log X box and set the x max to 6.65 and the y min to -200 and Y max to 0. For the second plot double press this and now select the Av to be plotted. From here also check the log x box, set the x axis to the same as for the phase plot and the Y max to 77. From here you should see the same as in the following picture
 
-<p align="center"> <img src="../../../media/module_1/OTA_images/ac_resp.png" width="800" height="700" /> </p>
+<p align="center"> <img src=".media/ac_resp.png" width="800" height="700" /> </p>
 
 Refer to the provided images and simulations to confirm the setup and ensure everything is correctly configured for the analysis.
 
@@ -353,7 +353,7 @@ After confirming the open-loop, you will introduce a second **OTA symbol** to te
 2. Connect the two inputs together
 
 By now you should have the following setup
-<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_5.png" width="1000" height="500" /> </p>
+<p align="center"> <img src=".media/tb_img_5.png" width="1000" height="500" /> </p>
 
 Now the code block should also have an extended definition where we will define our CMRR calculation as 
 
@@ -362,7 +362,7 @@ Now the code block should also have an extended definition where we will define
 
 ```
 Now you can add another graph window, or just use the XTerm terminal. You should now see a CMRR in the same region as the following image
-<p align="center"> <img src="../../../media/module_1/OTA_images/CMRR.png" width="500" height="500" /> </p>
+<p align="center"> <img src=".media/CMRR.png" width="500" height="500" /> </p>
 
 
 ### Step 9: Insert a Third OTA Symbol for PSRR Analysis
@@ -379,7 +379,7 @@ For the simulation setup, we refer to the description below
 3. For the supply now add a AC signal of 1 and a phase of 0
 
 For the setup it should something like this
-<p align="center"> <img src="../../../media/module_1/OTA_images/tb_img_6.png" width="700" height="600" /> </p>
+<p align="center"> <img src=".media/tb_img_6.png" width="700" height="600" /> </p>
 
 
 For the code block you can define the PSRR as given 
@@ -389,7 +389,7 @@ let PSRR = db(v(vout2)/v(VDDac))
 
 ```
 For the power supply rejection ratio you should see something like this:
-<p align="center"> <img src="../../../media/module_1/OTA_images/PSRR.png" width="500" height="500" /> </p>
+<p align="center"> <img src=".media/PSRR.png" width="500" height="500" /> </p>
 
 
 

modules/module_1_bandgap_reference/part_2_full_bgr/design_of_bgr.md

@@ -2,14 +2,14 @@
 
 In this tutorial, we will design a functional bandgap reference circuit and perform the necessary simulations to evaluate its performance. Our analysis will cover both the DC characteristics and transient behavior of the bandgap reference. Additionally, to understand the effects of mismatch, we will delve into the concept of mismatch analysis and conduct Monte Carlo simulations. Unlike the traditional BJT-based reference discussed in the introduction, the circuit we will design here uses an all-CMOS implementation. This approach leverages transistors M1 and M2 operating in weak inversion to achieve the desired performance.
 
-<p align="center"> <img src="../../../media/module_1/BGR_images/CMOS_bandgap.png" width="1000" height="900" /> </p>
+<p align="center"> <img src=".media/CMOS_bandgap.png" width="1000" height="900" /> </p>
 
 
 In the schematic above, we observe an all-CMOS bandgap reference circuit, which we will design in the following tutorial. As previously discussed in the introduction, achieving a temperature-dependent characteristic is essential to generate a CTAT (Complementary to Absolute Temperature) behavior in terms of current.
 
 For an NMOS transistor operating in the weak inversion (subthreshold) region, the current exhibits an exponential dependence on VGS​. This makes the NMOS transistor suitable for generating a CTAT characteristic, particularly because VGS​ varies with temperature.
 
-<p align="center"> <img src="../../../media/module_1/BGR_images/vgs_cmos.png" width="1000" height="900" /> </p>
+<p align="center"> <img src=".media/vgs_cmos.png" width="1000" height="900" /> </p>
 
 Similarly, by exploiting the voltage difference between the VGS​ values of transistors M1​ and M2​, we can generate a PTAT (Proportional to Absolute Temperature). 
 
@@ -62,7 +62,7 @@ Rppd’s low temperature coefficient, good precision, and moderate resistance ma
 
 First, we will build the core of the bandgap reference.
 
-<p align="center"> <img src="../../../media/module_1/BGR_images/bandgap_core.png" width="1000" height="700" /> </p>
+<p align="center"> <img src=".media/bandgap_core.png" width="1000" height="700" /> </p>
 
 As shown here, the setup is quite basic. You can adjust it to your needs, as long as the proper connections are maintained. The new component introduced is the RPPD resistors, which can be found in the components library under the PDK directory. Ensure the device sizes match those shown in the image, and don't forget to add a voltage source to supply VDD.
 
@@ -149,7 +149,7 @@ At this stage, you have two options for proceeding with the bandgap reference de
 
 The circuit, including the amplifier and startup circuitry, is shown in the image below. Ensure proper connections as depicted. Refer to the next section for details on setting up the testbench.
 
-<p align="center"> <img src="../../../media/module_1/BGR_images/OTA_amp.png" width="1000" height="600" /> </p>
+<p align="center"> <img src=".media/OTA_amp.png" width="1000" height="600" /> </p>
 
 
 ## Bandgap Reference Testbench
@@ -237,7 +237,7 @@ write bgr_transient.raw
 ### Final Schematic
 
 Ensure the schematic matches the design below:
-<p align="center"> <img src="../../../media/module_1/BGR_images/final_bandgap_core.png" width="1000" height="500" /> </p>
+<p align="center"> <img src=".media/final_bandgap_core.png" width="1000" height="500" /> </p>
 
 
 ### Visualizing Results
@@ -256,10 +256,10 @@ To visualize the results:
 Expected results should resemble the following plots:
 
 **Temperature Sweep (DC Simulation)**:
-<p align="center"> <img src="../../../media/module_1/BGR_images/dc_temp_plot.png" width="1000" height="900" /> </p>
+<p align="center"> <img src=".media/dc_temp_plot.png" width="1000" height="900" /> </p>
 
 **Transient Analysis**:
-<p align="center"> <img src="../../../media/module_1/BGR_images/tran_temp_plot.png" width="1000" height="900" /> </p>
+<p align="center"> <img src=".media/tran_temp_plot.png" width="1000" height="900" /> </p>
 
 
 ### Mismatch and Monte Carlo Simulations
@@ -436,7 +436,7 @@ value="
 
 From the written raw file the output is then plotted in python to extract the following result
 
-<p align="center"> <img src="../../../media/module_1/BGR_images/monte_carlo.png" width="700" height="500" /> </p>
+<p align="center"> <img src=".media/monte_carlo.png" width="700" height="500" /> </p>
 
 
 

modules/module_2_50GHz_MPA/part_1_biasing/.media/introduction.md

@@ -0,0 +1,25 @@
+# Tutorial: Setting Up a Workflow for RF Design with Open-Source Tools
+
+Welcome to this tutorial on setting up a comprehensive workflow for RF design using open-source tools. In this chapter, we will guide you through the design process of a **Medium Power Amplifier (MPA)** operating at **50 GHz**, covering key aspects and challenges encountered throughout the design and simulation stages.
+
+## Workflow Overview
+
+### 1. **DC Analysis with NGspice**
+We begin by setting up a simple **DC analysis** in **Ngspice** to evaluate the **biasing operation** of the MPA. This will allow us to determine the **stability factor** and ensure the amplifier operates within the desired parameters. Understanding the biasing conditions is crucial to ensure the amplifier functions efficiently at higher frequencies.
+
+### 2. **Input Matching with Qucs and NGspice**
+Next, we will focus on **input matching** using **Qucs-s**, still utilizing Ngspice for circuit simulation. Achieving proper impedance matching at the input is essential to maximize power transfer and minimize signal reflections, which is especially challenging at high frequencies like 50 GHz.
+
+### 3. **Output Matching and Non-Linear Behavior**
+For the **output matching**, we will explore the non-linear behavior of the MPA. As **NGspice** currently does not support non-linear analysis (as of April 2025), we will switch to using **Xyce**, a more advanced simulator capable of handling non-linear effects. This will allow us to simulate the amplifier's behavior under real-world conditions, including distortion and power saturation.
+
+### 4. **Data Extraction and Post-Processing**
+Once the simulations are complete, we will **extract the simulation data** from Qucs in CSV format and import it into **Jupyter Lab** for post-processing and plotting. Visualizing the data is essential for interpreting the amplifier's performance and making further design decisions.
+
+### 5. **EM Simulation with openEMS**
+As we extend the design, we will move on to the **layout realization** of the MPA. Here, we will perform **electromagnetic (EM) simulations** using **openEMS**, an open-source simulation tool for high-frequency circuits. We will use the **Python interface** developed by  [Volker Mühlhaus](https://muehlhaus.com/about) to set up and run the simulations (you can find more details on this in the provided tutorial). EM simulations help us understand the physical layout's impact on the amplifier's performance, including parasitic effects and signal integrity.
+
+### 6. **Final Remarks**
+Throughout this tutorial, we will cover the steps needed to create, simulate, and optimize a 50 GHz MPA using open-source tools
+
+Let’s dive into the details of each step! 

modules/module_2_50GHz_MPA/part_1_biasing/.media/schematic_bias_1

@@ -0,0 +1 @@
+

modules/module_2_50GHz_MPA/part_1_biasing/biasing_of_bjt.md

@@ -46,7 +46,7 @@ Next, search for **DC Voltage Source** and **two power sources**  and create a t
 
 
 
-<p align="center"> <img src="../../../media/module_2/schematic_bias_1.png" width="800" height="500" /> </p>
+<p align="center"> <img src=".media/schematic_bias_1.png" width="800" height="500" /> </p>
 
 
 Now, we need to set up our **analysis mode** and configure the necessary parameters to capture the circuit's behavior in the first step. This includes:
@@ -100,7 +100,7 @@ In the **SG13G2** technology, the **npn13G2** transistor has a maximum **current
     - To keep the testbench clean, open a new **.dpl** window to analyze results.
     - This format is used to display simulation data visually.
     - Click the **button with the following icon** (insert icon) to create it.
-      <img src="../../../media/module_2/dpl_window.png" width="30" height="30" /> </p>
+      <img src=".media/dpl_window.png" width="30" height="30" /> </p>
 3. **Add Visualization Elements**:
     - Navigate to the **Diagram** tab under **Components** and insert:
         - **Smith Chart** → Used to analyze **reflection coefficients** (**S11** and **S22**), which provide insight into the necessary impedance matching (ac.v(s_1_1),  ac.v(s_2_2)).
@@ -116,10 +116,10 @@ K = (1 - abs(s_1_1)^2 - abs(s_2_2)^2 + abs(s_1_1 * s_2_2 - s_1_2 * s_2_1)^2) / (
 When these steps are done, your schematic should look like the following:
 (remember to set the frequency in the elements that need it as we go !)
 And you results/.dpl file should look like the following:
-<p align="center"> <img src="../../../media/module_2/schematic_bias_2.png" width="800" height="600" /> </p>
+<p align="center"> <img src=".media/schematic_bias_2.png" width="800" height="600" /> </p>
 (remember to set the frequency in the elements that need it as we go !)
 And you results/.dpl file should look like the following:
-<p align="center"> <img src="../../../media/module_2/results_bias_1.png" width="800" height="500" /> </p>
+<p align="center"> <img src=".media/results_bias_1.png" width="800" height="500" /> </p>
 At this point we can add markers to the lines in order to analyze the results more precisely. 
 
 ## Finding the Optimal Number of Fingers
@@ -148,7 +148,7 @@ To make tuning easier, we will define the **resistor value as a parameter**. Thi
     - This will act as our first guess before fine-tuning through simulation.
 
 Once these steps are completed, your schematic should look like the following:
-<p align="center"> <img src="../../../media/module_2/schematic_bias_3.png" width="800" height="600" /> </p>
+<p align="center"> <img src=".media/schematic_bias_3.png" width="800" height="600" /> </p>
 ## Simulating and Fine-Tuning
 
 Now that the circuit is set up, we can proceed with the **simulation** and visualization of key parameters. Instead of using a **.dpl file**, we will directly add a **Smith chart** and a **Cartesian plot** to the testbench. These will allow us to observe:

modules/module_2_50GHz_MPA/part_1_biasing/schematic/bias_1_fingers/bias_1_fingers.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 25.1.0>
+<Qucs Schematic 24.4.1>
 <Properties>
-  <View=1122,-90,2432,618,1.14689,0,0>
+  <View=1094,-90,2460,648,1.10027,0,0>
   <Grid=10,10,1>
   <DataSet=bias_1_fingers.dat>
   <DataDisplay=bias_1_fingers.dpl>
@@ -16,7 +16,6 @@
 <Symbol>
 </Symbol>
 <Components>
-  <Pac P3 1 1360 370 18 -26 0 1 "1" 1 "50 Ohm" 1 "0 dBm" 0 "1 MHz" 0 "26.85" 0 "true" 0>
   <DCBlock C11 1 1520 270 -26 21 0 0 "1 uF" 0>
   <DCFeed L5 1 1600 320 20 -26 0 1 "1 uH" 0>
   <DCFeed L8 1 1780 50 20 -26 0 1 "1 uH" 0>
@@ -26,16 +25,17 @@
   <GND * 1 1600 440 0 0 0 0>
   <GND * 1 1820 270 0 0 0 0>
   <DCBlock C12 1 1990 100 -26 21 0 0 "1 uF" 0>
-  <Pac P4 1 2120 140 18 -26 0 1 "2" 1 "50 Ohm" 1 "0 dBm" 0 "1 MHz" 0 "26.85" 0 "true" 0>
   <GND * 1 2120 170 0 0 0 0>
   <GND * 1 1960 380 0 0 0 0>
   <Vdc V1 1 1960 330 18 -26 0 1 "1.65V" 1>
-  <NutmegEq NutmegEq1 1 1380 510 -28 16 0 0 "SP1" 1 "k=(1 - abs(s_1_1)^2 - abs(s_2_2)^2 + abs(s_1_1 * s_2_2 - s_1_2 * s_2_1)^2) / (2 * abs(s_1_2 * s_2_1))\n" 1>
   <INCLSCR INCLSCR2 1 1420 180 -60 16 0 0 ".LIB cornerHBT.lib hbt_typ\n" 1 "" 0 "" 0>
   <.SP SP1 1 1360 10 0 61 0 0 "lin" 1 "1 GHz" 1 "200 GHz" 1 "200" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0>
   <.DC DC1 1 1530 20 0 36 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
-  <Lib npn13G3 1 1780 270 10 64 0 0 "/home/pedersen/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "10" 1>
   <GND * 1 1780 450 0 0 0 0>
+  <Pac P3 1 1360 370 18 -26 0 1 "1" 1 "50 Ohm" 1 "0 dBm" 0 "50 GHz" 0 "26.85" 0 "true" 0>
+  <Pac P4 1 2120 140 18 -26 0 1 "2" 1 "50 Ohm" 1 "0 dBm" 0 "50 GHz" 0 "26.85" 0 "true" 0>
+  <Lib npn13G3 1 1780 270 10 64 0 0 "/home/pedersen/.qucs/user_lib/IHP_PDK_nonlinear_components" 0 "npn13G2" 0 "10" 1>
+  <NutmegEq NutmegEq1 1 1380 540 -28 16 0 0 "SP1" 1 "k=(1 - abs(s_1_1)^2 - abs(s_2_2)^2 + abs(s_1_1 * s_2_2 - s_1_2 * s_2_1)^2) / (2 * abs(s_1_2 * s_2_1))\n" 1>
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