Update sar_adc.md
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# SAR ADC
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In this section, we’ll dive into creating the final schematic for the SAR ADC. Since the design involves many components, the final testbench will be quite large, which means the transient simulation—our primary focus—will naturally be substantial. A good approach to building such a large design is to insert and verify each component one at a time. Although we will move quickly through the steps, it’s crucial for the reader to work through each stage carefully to ensure everything functions as intended.
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## Importing the SAR Algorithm
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Before diving into the full ADC schematic, it's essential to check whether the SAR algorithm can be simulated in the testbench. This can be done by copying the schematic from earlier in the module that uses mixed-signal simulation. You can then use this as the starting point for the rest of the schematic.
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> ⚠️ **Note:** Make sure to copy the shared object file (`.so`) and place it relative to the testbench, just like we did before. Create a simulation folder and include it there:
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>
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├── SAR_ADC_tb.sch
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├── simulations
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│ └── sar_logic.so
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└── xschemrc
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In this example, the wiring looks like this:
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<p align="center">
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<img src="../../../media/module_3/sar_algo_mixed_schem.png" width="900" height="700" />
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</p>
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Notice that the output numbering is reversed for B and BN because the first bit (i.e., B0 or BN0) will be flipped to represent the MSB. It’s recommended to apply some test signals to this block to ensure that it compiles and runs correctly.
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### S/H, Comparator, and C-DAC
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Next, we import the bootstrap switch, comparator, and C-DAC, which will form the core of the ADC. These components are implemented as follows:
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<p align="center">
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<img src="../../../media/module_3/adc_core.png" width="900" height="900" />
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</p>
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The labeling can be done in any way that suits your design preferences.
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## Switch Bank
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Now, we connect the switch bank to the C-DAC and label it according to the outputs from the SAR algorithm. The wiring setup is shown below:
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<p align="center">
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<img src="../../../media/module_3/SAR_ADC_setup.png" width="900" height="900" />
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</p>
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## Defining Signals and Biasing
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At this stage, we need to define the biasing and signals used in the system. Below are the configurations for various components:
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1. **Comparator Bias (bias):**
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```
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value=0.6
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```
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2. **Sampling Clock (clk_samp):**
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```
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"dc 0 ac 0 PULSE(0 1.2 0 10p 10p T_half T)"
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```
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3. **Vdd (Vdd):**
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```
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value=1.2
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```
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4. **Comparator Clock (clk_comp):**
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```
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"dc 0 ac 0 PULSE(0 1.2 comparator_delay 10p 10p T_algo_PW T_algo)"
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```
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5. **Positive Input to ADC (vin_pos):**
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```
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value=0.8
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```
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6. **Negative Input to ADC (vin_neg):**
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```
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value=0.4
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```
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7. **Clock for Postprocessing (dac_clk):**
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```
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"dc 0 ac 0 PULSE(0 1.2 DAC_delay 10p 10p DAC_PW T)"
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```
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These signals are configured as shown below:
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<p align="center">
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<img src="../../../media/module_3/source_setup.png" width="900" height="900" />
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</p>
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To generate the clock for the algorithm, we use a NAND gate connected to the output of the comparator. This creates a "valid" signal when one output is high and the other is low. The connection is as follows:
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<p align="center">
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<img src="../../../media/module_3/nand_con.png" width="900" height="900" />
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</p>
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## Code Blocks
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Now we’re ready to define the simulation code blocks. As always, we start by creating the code block for the models:
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```
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name=MODEL only_toplevel=true
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format="tcleval( @value )"
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value=".lib cornerMOSlv.lib mos_tt
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.lib $::SG13G2_MODELS/cornerCAP.lib cap_typ
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"
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```
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Next, we define the simulation code block by setting the simulation parameters and running the transient analysis:
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```
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name=NGSPICE only_toplevel=true
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value="
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.param temp=27
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.param T = 1u
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.param T_half = T/2
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.param T_algo = T/16
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.param T_algo_delay = T/10
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.param T_algo_PW = T/32
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.param DAC_delay = 0.99*T
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.param DAC_PW = T/20
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.param comparator_delay = 0.328*T
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.control
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tran 1u 8u
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let vin_diff = v(Vin_pos) - v(Vin_neg)
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let comp_diff = v(op)- v(om)
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write sar_adc_test.raw
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.endc
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"
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```
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### Code Explanation:
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1. **Simulation Parameters:**
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- `.param temp=27` sets the temperature to 27°C.
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- `.param T = 1u` defines the base time period `T` as 1 µs.
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- `.param T_half = T/2` defines half of `T`.
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- `.param T_algo = T/16` is the time period for the algorithm (16 times smaller than `T`).
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- `.param T_algo_delay = T/10` sets the delay for the algorithm to 1/10 of `T`.
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- `.param T_algo_PW = T/32` defines the pulse width of the algorithm clock.
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- `.param DAC_delay = 0.99*T` defines the DAC delay as 99% of `T`.
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- `.param DAC_PW = T/20` defines the DAC pulse width.
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- `.param comparator_delay = 0.328*T` defines the comparator delay.
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2. **Simulation Control:**
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- `.control` starts the simulation block.
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- `tran 1u 8u` specifies a transient analysis with a step size of 1 µs and a total simulation time of 8 µs.
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- `let vin_diff = v(Vin_pos) - v(Vin_neg)` computes the differential voltage between the positive and negative inputs to the ADC.
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- `let comp_diff = v(op) - v(om)` computes the difference between the output of the comparator.
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- **write sar_adc_test.raw** saves the data in binary format under simulation so it can be used for plotting the data in Xschem
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3. **End of Simulation:**
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- `.endc` marks the end of the control block, completing the simulation setup.
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## Running the Simulation
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Below, the clock waveforms are shown. As seen, the sampling phase ends when `clk_samp` goes low, which then triggers the comparator. This firing of the comparator generates a rising edge on `clk_algo`, initiating the SAR conversion. Since the `reset (rst)` signal is connected to the sampling clock and `Enable (En)` is tied to `Vdd` (i.e., always logic high), the SAR logic responds to the `clk_algo` signal (the output of the NAND gate) and begins the bit-wise comparison process.
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> **Note:** The comparator performs comparisons on the **falling edge**, not the rising edge.
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After the 8th comparison (i.e., once all bits are resolved), the `DAC_clk` signal is triggered. This clock is later used in post-processing when an ideal DAC is implemented in Python.
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<p align="center">
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<img src="../../../media/module_3/clks_conversion.png" width="900" height="900" />
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</p>
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<p align="center">
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<img src="../../../media/module_3/clocks_last_convertion.png" width="900" height="900" />
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</p>
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Looking at the voltage across the C-DAC during the conversion phase, we observe the following waveform:
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<p align="center">
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<img src="../../../media/module_3/cdac_conversion.png" width="900" height="900" />
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</p>
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This confirms that the SAR conversion is functioning correctly.
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---
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## Further Analysis
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At this point, we have a working SAR ADC, so the primary tutorial goal is achieved. However, we will now extend the analysis by extracting the output and post-processing it in Python to recover the ADC's differential input waveform.
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To do this, we’ll apply a differential sinusoidal input and make minor modifications to our simulation setup.
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### Modified Input Sources
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We apply two sinusoidal sources 180° out of phase:
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1. **Positive Input to ADC (`vin_pos`):**
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```
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"dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 0)"
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```
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**Negative Input to ADC (`vin_neg`):**
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```
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"dc 0 ac 0 SIN(0.6 0.3 12.7k 0 0 180)"
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```
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With this configuration, we expect the differential input to be a sinusoidal waveform of 12.7 kHz.
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### Updated NGspice Simulation Block
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We'll also update the transient simulation command to run longer and collect more samples. Additionally, to avoid creating an extremely large binary waveform file (which could exceed 20 GB), we'll directly export selected signals to a text file for external processing:
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```
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"
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.param temp=27
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.param T = 1u
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.param T_half = T/2
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.param T_algo = T/16
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.param T_algo_delay = T/10
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.param T_algo_PW = T/32
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.param DAC_delay = 0.99*T
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.param DAC_PW = T/20
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.param comparator_delay = 0.328*T
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.control
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tran 1u 320u
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let vin_diff = v(Vin_pos) - v(Vin_neg)
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let comp_diff = v(op)- v(om)
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set wr_singlescale
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set wr_vecnames
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wrdata bit_data.txt D0 D1 D2 D3 D4 D5 D6 D7 vin_diff dac_clk
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.endc
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"
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```
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The lines:
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```
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set wr_singlescale
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set wr_vecnames
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wrdata bit_data.txt D0 D1 D2 D3 D4 D5 D6 D7 vin_diff dac_clk
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```
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The extracted data comes directly from the SAR logic and includes:
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- The 8 output bits (`D0`–`D7`)
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- The differential input voltage (`vin_diff`)
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- The DAC clock signal (`dac_clk`), which serves as a virtual clock for reconstructing the analog output using an ideal DAC in Python.
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These signals are saved into a text file during the simulation and can be post-processed externally. In the directory:
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```
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module_3_8_bit_SAR_ADC/part_4_SAR_ADC/scripting
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```
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you will find a Jupyter Notebook that loads this data and reconstructs the analog signal using a Python function called `virtual_dac`.
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### Example Dataframe from JupyterLab
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When the `bit_data.txt` is imported, the dataframe looks as follows:
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<p align="center">
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<img src="../../../media/module_3/jupyter_lab_data.png" width="900" height="900" />
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</p>
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### The `virtual_dac()` Function
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Here is the key function used to reconstruct the analog signal from the digital SAR output:
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```
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def virtual_dac(df, vmin=-1.2, vmax=1.2, vdd=1.2, vss=0.0,
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thresh=None, dir=1, td=0, tt=0):
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if thresh is None:
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thresh = (vdd + vss) / 2.0
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# Verilog-A bit order: i1 (LSB) to i8 (MSB)
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bits = ['D0', 'D1', 'D2', 'D3', 'D4', 'D5', 'D6', 'D0'] # D0 is MSB in your DF
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fullscale = vmax - vmin
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clk = df['dac_clk'].values
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time = df['time'].values
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output = np.zeros(len(df))
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prev_clk = clk[0]
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aout = 0
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for i in range(len(df)):
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clk_edge = False
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if dir == 1 and prev_clk <= thresh and clk[i] > thresh:
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clk_edge = True # Rising edge
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elif dir == -1 and prev_clk >= thresh and clk[i] < thresh:
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clk_edge = True # Falling edge
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if clk_edge or i == 0: # i == 0 handles initial_step
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aout = 0
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weight = 2
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for bit in bits:
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if df[bit].iloc[i] > thresh:
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aout += fullscale / weight
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weight *= 2
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output[i] = aout + vmin
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else:
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output[i] = output[i - 1] # Hold previous value
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prev_clk = clk[i]
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return output
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```
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### Parameters
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- `vmin` and `vmax`: Define the full differential range of the DAC.
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- `vdd` and `vss`: Define the power supply range.
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- `thresh`: Optional threshold; defaults to `(vdd + vss) / 2`.
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- `dir`: Clock edge direction (1 for rising, -1 for falling).
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### Results
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If the Ngspice simulation was successful, the `vin_diff` plot should look like:
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<p align="center">
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<img src="../../../media/module_3/vin_diff.png" width="900" height="900" />
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</p>
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And the reconstructed output from the ideal DAC will appear as:
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<p align="center">
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<img src="../../../media/module_3/SAR_ADC_output.png" width="900" height="900" />
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</p>
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## Conclusion
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This post-processing step demonstrates how to extract and visualize the SAR ADC output. The setup also forms a solid foundation for further analysis, such as computing dynamic performance metrics of the ADC—SNR, SINAD, and ENOB—using standard Python libraries.
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