Update digital_comps.md
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# Digital Components
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In this section, we will implement several essential digital components required for the SAR ADC. These include:
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- **SAR Algorithm**: The control logic responsible for managing the successive approximation process during analog-to-digital conversion.
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- **Bootstrap Switch**: Used for sampling the input voltage onto the C-DAC with minimal distortion and high linearity.
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- **Transmission Gate**: Employed to switch the bottom plates of the capacitors in the C-DAC.
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- **NAND Gate**: Utilized to generate control signals such as the SAR clock.
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We will begin by focusing on the **SAR algorithm** and integrating it into Xschem for performing mixed-signal simulations. This integration can be complex, but the provided module offers a working setup to help you get started. In the following, we will break down this setup and its file structure.
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## Understanding the File Structure
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Navigate to the following folder:
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```
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module_3_8_bit_SAR_ADC/part_2_digital_comps
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```
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Inside the `algorithm` directory, you will find all necessary files for simulating and compiling the SAR algorithm. Let’s start by reviewing the Verilog code for the SAR logic:
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```
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module sar_logic (
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input wire clk,
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input wire Op,
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input wire En,
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input wire Om,
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input wire rst,
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output reg [6:0] B, // 7-bit
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output reg [6:0] BN, // 7-bit
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output reg [7:0] D // 8-bit
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);
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reg [3:0] counter = 4'b0000; // 4-bit counter
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always @(posedge clk) begin
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if (rst) begin
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B <= 7'b0000000;
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BN <= 7'b0000000;
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D <= 8'b00000000;
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counter <= 4'b0000;
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end else if (En && (Op ^ Om)) begin
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if (counter < 7) begin
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D <= D | ({7'b0, Op} << counter);
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B[counter % 7] <= (Op) ? 1'b1 : 1'b0;
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BN[counter % 7] <= (Om) ? 1'b1 : 1'b0;
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counter <= counter + 1'b1;
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end
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end
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end
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endmodule
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```
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### Code Explanation
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This Verilog module describes a simple synchronous SAR algorithm that operates on the **positive edge of the clock**. The two comparator outputs, `Op` and `Om`, represent complementary decision signals at each iteration.
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- `Op` is high if the input is greater than the DAC value.
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- `Om` is high if the input is less than the DAC value.
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- The output `D` stores the 8-bit final result of the SAR conversion.
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- `B` and `BN` store intermediate bits of the decision logic in direct and inverted form, respectively.
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- A 4-bit `counter` tracks the current bit being decided.
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- The logic ensures only one bit decision is taken per clock cycle.
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The next Verilog related file you will see is a simple testbench for the Verilog code which will not be shown here since this can easily be modified.
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## Supporting Files
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### `conf.gtkw` – GTKWave Configuration
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This file configures the GTKWave waveform viewer to automatically load the relevant signals and layout. It includes the following lines:
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```
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[*]
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[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
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[*] Mon Sep 30 13:11:15 2024
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[*]
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[dumpfile] "sar_logic_tb.vcd"
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[dumpfile_mtime] "Mon Sep 30 13:10:47 2024"
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[dumpfile_size] 777
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[savefile] "conf.gtkw"
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[timestart] 0
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[size] 1906 985
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[pos] -1 -1
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*-14.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 269
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[signals_width] 102
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[sst_expanded] 1
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[sst_vpaned_height] 291
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@28
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sar_logic_tb.Op
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sar_logic_tb.Om
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sar_logic_tb.B[6:0]
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sar_logic_tb.BN[6:0]
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sar_logic_tb.D[7:0]
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sar_logic_tb.clk
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sar_logic_tb.rst
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sar_logic_tb.En
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@29
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[pattern_trace] 1
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[pattern_trace] 0
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```
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This ensures that all key signals are pre-loaded when you open GTKWave, allowing you to quickly inspect the SAR algorithm’s behavior.
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### `Makefile` – Automation and Simulation
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The `Makefile` provides automation for compiling, simulating, viewing waveforms, and generating mixed-signal compatible modules. Here's a breakdown of its targets:
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```
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# Define variables
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IVERILOG = iverilog
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VVP = vvp
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GTKWAVE = gtkwave
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NGSPICE = ngspice
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OUTPUT = sar_logic.out
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MIXED = sar_logic.so
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MIXED_OBJ = sar_logic_obj_dir
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VCD_FILE = sar_logic_tb.vcd
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SRC_FILES = sar_logic.v sar_logic_tb.v
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NGSPICE_FILE = sar_logic.v
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DEST_DIR = ../xschem/simulations
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# Default target
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all: run_wave
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# Compile using iverilog
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$(OUTPUT): $(SRC_FILES)
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$(IVERILOG) -o $(OUTPUT) $(SRC_FILES)
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# Run the simulation with vvp
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run: $(OUTPUT)
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$(VVP) $(OUTPUT)
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copy:
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cp $(MIXED) $(DEST_DIR)
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# Open the wave file in GTKWave
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wave: $(VCD_FILE)
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$(GTKWAVE) $(VCD_FILE) conf.gtkw
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# Run ngspice vlnggen command
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ngspice:
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$(NGSPICE) vlnggen $(NGSPICE_FILE)
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# Execute both the simulation and wave viewer
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run_wave: run wave
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# Run ngspice and then the rest of the steps
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full: ngspice run_wave copy
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# Clean up generated files
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clean:
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rm -f $(OUTPUT) $(VCD_FILE) $(MIXED)
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rm -rf $(MIXED_OBJ)
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```
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in the defined variables you can follow the same structure for any given code, the most essential is the dump files, shared object file used for simulation (**.so**) and ofcourse the src_files.
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#### Targets:
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- `all` → Runs the full simulation and waveform view (`run_wave`).
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- `$(OUTPUT)` → Compiles the Verilog files using Icarus Verilog.
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- `run` → Executes the compiled simulation, generating a `.vcd` file.
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- `wave` → Opens the `.vcd` waveform in GTKWave with the saved config.
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- `run_wave` → Combines both `run` and `wave`.
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- `ngspice` → Generates the `.so` file for use in mixed-signal simulations with Xschem/Ngspice using `vlnggen`.
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- `copy` → Copies the `.so` file to the appropriate Xschem simulation folder.
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- `full` → Executes all steps: create `.so`, simulate, view, and copy.
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- `clean` → Cleans all generated files including `.out`, `.vcd`, `.so`, and intermediate directories.
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```
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make run_wave # Compile and open wave viewer
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make full # Full build including mixed-signal export and copy
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make clean # Clean up simulation artifacts
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```
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Now at this point you can write *make full*. And this should compile the Verilog code and give you the following view:
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<p align="center">
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<img src="../../../media/module_3/wave_viewer.png" width="900" height="500" />
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</p>
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From here, you can modify the testbench to observe different behaviors or expand the `sar_logic_tb` hierarchy in GTKWave to explore the available signal waveforms.
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## Creating the Symbol for Mixed-Signal Simulation
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The next step is to create a symbol for use in mixed-signal simulations with Xschem. This process can be particularly tricky, as it requires correct syntax and precise ordering of pins. To simplify this, a Python script has been provided specifically for generating a symbol for `sar_logic.v`.
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> ⚠️ Note: This script is tailored to the `sar_logic.v` module and may not work for other designs without modification.
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### Running the Symbol Generation Script
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Navigate to the Python folder located at:
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```
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part_2_digital_comps/algorithm/python
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```
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The script is invoked as follows:
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```
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Usage: python generate_sym.py <verilog_file> <symbol_file>
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Example: python generate_sym.py control.v test.sym
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```
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For our case, run:
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```
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python3 generate_sym.py ../verilog/sar_logic.v ../xschem/sar_logic.sym
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```
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You should see output similar to:
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```
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Parsed module: sar_logic
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Inputs: ['clk', 'Op', 'En', 'Om', 'rst']
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Outputs: ['D7', 'D6', 'D5', 'D4', 'D3', 'D2', 'D1', 'D0', 'BN6', 'BN5', 'BN4', 'BN3', 'BN2', 'BN1', 'BN0', 'B6', 'B5', 'B4', 'B3', 'B2', 'B1', 'B0']
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Xschem symbol written to ../xschem/sar_logic.sym
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```
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You can now navigate to the `xschem` folder and view the newly generated symbol:
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<p align="center">
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<img src="../../../media/module_3/sar_algo_symbol.png" width="500" height="900" />
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</p>
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> ⚠️ Note: In the make file the location for the shared object file `(.so)` was specified as in the simulations folder generated by xschem, this is needed for the mixed signal simulation.
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## Preparing the Mixed-Signal Testbench
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Inside the same `xschem` directory, you will also find two additional symbols:
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- `adc_bridge1.sym`: Converts analog input into digital signals compatible with the SAR logic.
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- `dac_bridge1.sym`: Converts digital output from the SAR logic into analog signals for NGSpice.
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These bridges are essential for enabling mixed-signal simulation in NGSpice.
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With everything set up, you can now build a testbench using the generated `sar_logic.sym` and the two bridge components:
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<p align="center">
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<img src="../../../media/module_3/sar_algo_tb.png" width="900" height="600" />
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</p>
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## Stimuli and Simulation Setup
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The following PULSE sources are used to simulate signal transitions:
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- **Op**:
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```
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name=V6 value="dc 0 ac 0 PULSE(1.2 0 100u 1n 1n 500u 1m)"
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```
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- **Om**:
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```
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"dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 500u 1m)"
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```
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- **En**:
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```
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"dc 0 ac 0 PULSE(1.2 0 0 1n 1n 30u 1m)"
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```
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- **clk**:```
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"dc 0 ac 0 PULSE(0 1.2 0 10p 10p 5u 10u)"
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- **rst**:
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```
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"dc 0 ac 0 PULSE(0 1.2 100u 1n 1n 10u 1m)"
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```
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For simulation, a transient analysis is defined:
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```
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name=NGSPICE only_toplevel=true
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value="
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.param temp=27
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.control
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save all
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tran 1u 200u
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write sar_logic.raw
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.endc
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"
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```
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Once everything is in place, you can run the simulation. The waveform output should resemble the one below:
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<p align="center">
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<img src="../../../media/module_3/mixed_signal_output.png" width="900" height="700" />
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</p>
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## What's Next?
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You are encouraged to experiment with the input signals, change timings, and verify the results against the standalone Verilog testbench. This is a great way to gain intuition about how the SAR logic behaves in a mixed-signal context.
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## Bootstrap - Switch
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Explain the function of bootstrap switch
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In this design the bootstrap switch that was used is a modification of the one seen below:
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<p align="center">
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<img src="../../../media/module_3/boot_Strap_schematic.png" width="900" height="550" />
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</p>
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the schematic for the boostrap can be seen in the following image
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<p align="center">
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<img src="../../../media/module_3/bootstrap_switch_xschem.png" width="900" height="550" />
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</p>
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The dimensions of the transistors and caps are in reference to the schematic in xschem.
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**NMOS Transistors (`sg13_lv_nmos`):**
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- M1: W = 1.3 µm, L = 0.13 µm, ng = 1, m = 1
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- M2: W = 1.3 µm, L = 0.13 µm, ng = 1, m = 1
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- M3: W = 1.3 µm, L = 0.13 µm, ng = 1, m = 1
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- M5: W = 3.0 µm, L = 0.13 µm, ng = 1, m = 1
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- M7: W = 3.0 µm, L = 0.13 µm, ng = 1, m = 1
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- M8: W = 5.0 µm, L = 0.13 µm, ng = 1, m = 1
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- M9: W = 5.0 µm, L = 0.13 µm, ng = 1, m = 1
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- M10: W = 0.5 µm, L = 0.13 µm, ng = 1, m = 1
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- M11: W = 0.5 µm, L = 0.13 µm, ng = 1, m = 1
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- M12: W = 1.3 µm, L = 0.13 µm, ng = 1, m = 1
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**PMOS Transistors (`sg13_lv_pmos`):**
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- M4: W = 0.5 µm, L = 0.13 µm, ng = 1, m = 1
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- M6: W = 0.5 µm, L = 0.13 µm, ng = 1, m = 1
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**Capacitors (`cap_cmim`):**
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- C1: W = 4.665 µm L = 6.99 µm m = 1
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- C5: W = 4.665 µm L = 6.99 µm m = 1
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- C6: W = 11.485 µm L = 11.485 µm m = 1
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For the inverter the reader is needed to design this use the following parameters
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**NMOS Transistors (`sg13_lv_nmos`):**
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- M1: W = 1.3 µm, L = 0.4 µm, ng = 1, m = 1
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**PMOS Transistors (`sg13_lv_pmos`):**
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- M2: W = 1.3 µm, L = 0.8 µm, ng = 1, m = 1
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From here the symbol can be made. It was done in the following way:
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<p align="center">
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<img src="../../../media/module_3/bootstrap_sym.png" width="700" height="500" />
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</p>
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## Testing the Bootstrap Switch
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The next step is to evaluate the **transient behavior** of the bootstrap switch. For this purpose, the following testbench was created:
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<p align="center">
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<img src="../../../media/module_3/boot_strap_tb.png" width="550" height="650" />
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</p>
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A simple transient analysis was performed with the following input stimuli:
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- **Clock (clk):**
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```
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name=V1 value="PULSE(0 5 0 1n 1n 0.5u 1u)"
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```
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- **Input Voltage (vin):**
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```
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name=V2 value="SIN(0.6 0.6 16e3 0 0 0)"
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```
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According to the documentation, the syntax for a sinusoidal source is:
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```
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SIN(VO VA FREQ TD THETA PHASE)
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```
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In this case, the input is a very low-frequency signal, which is acceptable for now. The rest of the testbench is fairly self-explanatory, so we proceed directly to the simulation. The resulting output is shown below:
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<p align="center">
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<img src="../../../media/module_3/boot_Strap_output_tran.png" width="750" height="700" />
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</p>
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An interesting next step would be to evaluate **SNR, SINAD, and ENOB** based on the simulation output. To extract the necessary waveform data, you can use the following script within the code block:
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```
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name=NGSPICE
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only_toplevel=true
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value="
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.control
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save all
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tran 1u 200u
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set wr_singlescale
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set wr_vecnames
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write test_bootstrap.raw
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wrdata vout_data.txt v(vo)
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.endc
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"
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```
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## Logic Gates
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For generating the clock required by the SAR algorithm and applying logic to the C-DAC, we need basic **logic gates** such as NAND and transmission gates.
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### NAND Gate
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The schematic of a CMOS NAND gate is straightforward and is shown below:
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<p align="center">
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<img src="../../../media/module_3/nand_gate_logic.png" width="900" height="600" />
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</p>
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[Image Source](https://www.allaboutelectronics.org/cmos-logic-gates-explained/)
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The corresponding Xschem implementation:
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<p align="center">
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<img src="../../../media/module_3/Nand_gate.png" width="900" height="900" />
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</p>
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Transistor sizing used:
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**NMOS Transistors (`sg13_lv_nmos`):**
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|
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- M: W = 0.25 µm L = 0.13 µm ng = 1 m = 1
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**PMOS Transistors (`sg13_lv_pmos`):**
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- M2: W = 0.5 µm L = 0.13 µm ng = 1 m = 1
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The corresponding symbol:
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<p align="center">
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<img src="../../../media/module_3/nand_sym.png" width="700" height="400" />
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</p>
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![[nand_sym.png]]
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||||
You can find the testbench under:
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|
||||
```
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part_2_digital_comps/nand_gate/testbench
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|
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```
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At this point in the module, the testbench setup should be fairly straightforward to follow.
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## Transmission Gate
|
||||
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||||
The **transmission gate** is a critical component in this design, as it delivers digital logic signals to the C-DAC. Its schematic is shown here:
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<p align="center">
|
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<img src="../../../media/module_3/transmission_gate_schem.png" width="600" height="300" />
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</p>
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The Xschem implementation:
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<p align="center">
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||||
<img src="../../../media/module_3/T_gate_xschem.png" width="600" height="500" />
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||||
</p>
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||||
|
||||
Transistor sizing:
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||||
|
||||
**NMOS Transistors (`sg13_lv_nmos`):**
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||||
|
||||
- M: W = 1.0 µm L = 0.13 µm ng = 1 m = 1
|
||||
|
||||
|
||||
**PMOS Transistors (`sg13_lv_pmos`):**
|
||||
|
||||
- M2: W = 2.0 µm L = 0.13 µm ng = 1 m = 1
|
||||
|
||||
|
||||
Corresponding symbol:
|
||||
<p align="center">
|
||||
<img src="../../../media/module_3/Transmission_gate_sym.png" width="600" height="500" />
|
||||
</p>
|
||||
|
||||
### Testbench for Transmission Gate as Switch
|
||||
|
||||
To test the transmission gate in a switching configuration, the following testbench was created:
|
||||
|
||||
<p align="center">
|
||||
<img src="../../../media/module_3/T_gate_switch_schem.png" width="550" height="600" />
|
||||
</p>
|
||||
|
||||
Here, the transmission gate passes either **Vref/Vdd** or **GND**, depending on the control signal. The testbench schematic:
|
||||
<p align="center">
|
||||
<img src="../../../media/module_3/xschem_tb_trans_switch.png" width="700" height="850" />
|
||||
</p>
|
||||
|
||||
- **Vdd** is set to 1.2 V
|
||||
|
||||
- **Vref** is 0.6 V (arbitrarily chosen)
|
||||
|
||||
|
||||
The control pulse is defined as:
|
||||
```
|
||||
name=V2 value="PULSE(0 1.2 0 1u 1u 10u 20u)"
|
||||
```
|
||||
After simulation, the results should resemble the following:
|
||||
<p align="center">
|
||||
<img src="../../../media/module_3/transmission_gate_switch_result.png" width="900" height="600" />
|
||||
</p>
|
||||
|
||||
As observed, when the control signal is high, the output is grounded; when low, it passes Vref.
|
||||
Loading…
Reference in New Issue