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change markdwon

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PhillipRambo 2025-05-13 09:17:36 +02:00
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modules/module_3_8_bit_SAR_ADC/part_1_comparator/comparator.md
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@ -168,7 +168,7 @@ Looking at the model includes, we see that now have defined the mismatch model
name=MODEL1 only_toplevel=false
format="tcleval( @value )"
value="
.lib cornerMOSlv.lib mos_tt_mismatch
.lib cornerMOSlv.lib mos_tt_stat
"
```
This model includes variations in transistor parameters to simulate the effects of mismatches in the fabrication process. These variations are then used to analyze the impact on the comparator’s behavior.