Just a note that post-synthesis simulation also has to be explained

Aleks-Daniel Jakimenko-Aleksejev 2016-11-08 11:15:46 +02:00
parent e17e8807db
commit 071dcfc856
1 changed files with 4 additions and 1 deletions

@ -6,12 +6,15 @@ That being said, most of your workflow can still be done using Yosys, Icarus Ver
This page will show how to get commonly used Vivado functionality with Yosys.
# Testing
# Simulation
TODO
# Wave Viewer
TODO
# Post-Synthesis Simulation
TODO
# Elaborated Design Schematic / RTL Schematic
All you have to do is load your Verilog source files and run [``prep``](http://www.clifford.at/yosys/cmd_prep.html). Then, use [``show``](http://www.clifford.at/yosys/cmd_prep.html) to see parts that are of any interest to you. You probably also want to use ``-colors`` and ``-stretch`` flags to make the graph a bit more readable.