diff --git a/Migrating-from-Vivado.md b/Migrating-from-Vivado.md
index 9d56291..ffca0ef 100644
--- a/Migrating-from-Vivado.md
+++ b/Migrating-from-Vivado.md
@@ -6,12 +6,15 @@ That being said, most of your workflow can still be done using Yosys, Icarus Ver
 
 This page will show how to get commonly used Vivado functionality with Yosys.
 
-# Testing
+# Simulation
 TODO
 
 # Wave Viewer
 TODO
 
+# Post-Synthesis Simulation
+TODO
+
 # Elaborated Design Schematic / RTL Schematic
 All you have to do is load your Verilog source files and run [``prep``](http://www.clifford.at/yosys/cmd_prep.html). Then, use [``show``](http://www.clifford.at/yosys/cmd_prep.html) to see parts that are of any interest to you. You probably also want to use ``-colors`` and ``-stretch`` flags to make the graph a bit more readable.