From 071dcfc856344525405311cdc53b38faf383cbcf Mon Sep 17 00:00:00 2001 From: Aleks-Daniel Jakimenko-Aleksejev Date: Tue, 8 Nov 2016 11:15:46 +0200 Subject: [PATCH] Just a note that post-synthesis simulation also has to be explained --- Migrating-from-Vivado.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Migrating-from-Vivado.md b/Migrating-from-Vivado.md index 9d56291..ffca0ef 100644 --- a/Migrating-from-Vivado.md +++ b/Migrating-from-Vivado.md @@ -6,12 +6,15 @@ That being said, most of your workflow can still be done using Yosys, Icarus Ver This page will show how to get commonly used Vivado functionality with Yosys. -# Testing +# Simulation TODO # Wave Viewer TODO +# Post-Synthesis Simulation +TODO + # Elaborated Design Schematic / RTL Schematic All you have to do is load your Verilog source files and run [``prep``](http://www.clifford.at/yosys/cmd_prep.html). Then, use [``show``](http://www.clifford.at/yosys/cmd_prep.html) to see parts that are of any interest to you. You probably also want to use ``-colors`` and ``-stretch`` flags to make the graph a bit more readable.