nella 90e281a964 Reject abc9 boxes without an input or an output.

2026-09-21 16:58:03 +02:00

..

librelane

Mark cells as imported correctly.

2026-09-21 16:57:58 +02:00

openroad

Don't mark cells w no unput as boxes.

2026-09-21 16:58:03 +02:00

box_no_input.ys

Reject abc9 boxes without an input or an output.

2026-09-21 16:58:03 +02:00

box_no_output.ys

Reject abc9 boxes without an input or an output.

2026-09-21 16:58:03 +02:00

bug2530.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug4291.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug4689.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug5220.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug5223.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug5445.lib

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug5445.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

bug6179.ys

Add issue regressions.

2026-09-21 16:33:47 +02:00

cells.genlib

Test port corner cases.

2026-09-21 16:33:47 +02:00

comb_equiv.ys

Add abc_new tests.

2026-09-21 16:33:47 +02:00

dup_inv.lib

Repro option accumulation.

2026-09-21 16:33:47 +02:00

duplicate_cell_libs.ys

Expect abc error.

2026-09-21 16:39:09 +02:00

edge_cases.ys

Test port corner cases.

2026-09-21 16:33:47 +02:00

generate_mk.py

Clean up after bufnorm.

2026-09-21 16:57:53 +02:00

genlib_equiv.ys

Test port corner cases.

2026-09-21 16:33:47 +02:00

hier_check.ys

Clean up after bufnorm.

2026-09-21 16:57:53 +02:00

init_attr.ys

Test boundary cells.

2026-09-21 16:33:47 +02:00

keep_wire.ys

Keep keep wires in abc.

2026-09-21 16:57:41 +02:00

latch_boundary.ys

Test boundary cells.

2026-09-21 16:33:47 +02:00

mixed_cells_normal_lib.ys

Test hierarchy and selections.

2026-09-21 16:33:47 +02:00

multiclk_equiv.ys

Test boundary cells.

2026-09-21 16:33:47 +02:00

paramod_equiv.ys

Test hierarchy and selections.

2026-09-21 16:33:47 +02:00

partial_box_ports.ys

Port OpenROAD cut tests.

2026-09-21 16:33:47 +02:00

scopeinfo.ys

Keep scopeinfo.

2026-09-21 16:57:41 +02:00

script_inline.ys

Test port corner cases.

2026-09-21 16:33:47 +02:00

selection.ys

Test hierarchy and selections.

2026-09-21 16:33:47 +02:00

tribuf_boundary.ys

Test boundary cells.

2026-09-21 16:33:47 +02:00

twice.ys

Repro option accumulation.

2026-09-21 16:33:47 +02:00

whitebox_equiv.ys

Don't divide by zero with zero delays.

2026-09-21 16:57:41 +02:00

whitebox_no_timing.ys

Don't divide by zero with zero delays.

2026-09-21 16:57:41 +02:00

wide_ports_equiv.ys

Test port corner cases.

2026-09-21 16:33:47 +02:00