yosys/passes
Akash Levy 768f2aa00b
Merge pull request #139 from Silimate/sim
Add log-interval
2026-04-02 15:24:24 -07:00
..
cmds Merge from main 2026-02-13 04:14:08 -08:00
equiv Bump to latest 2025-09-21 01:10:04 -07:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy Merge remote-tracking branch 'upstream/main' 2025-11-07 01:42:20 -08:00
memory Fix cell naming issues 2026-02-13 01:05:51 -08:00
opt Improve wreduce runtime 2026-02-19 01:03:26 -08:00
pmgen More minor cleanup 2025-09-28 07:19:53 -07:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat greptile 2026-04-02 11:15:39 -07:00
silimate opt_shift 2026-04-02 00:43:06 -07:00
techmap Removed -filter_non_trigger_outputs functionality 2026-03-31 10:12:21 -07:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00