yosys/tests/arch at 66b2fdc8e4246a9f4f7aaa2c2dd8db01fc4d2942 - yosys - Gitea: Git with a cup of tea

luke/yosys

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Emil J. Tywoniak 9d93aa275a tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

..

Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7

2026-07-09 08:46:46 +00:00

synth_anlogic: remove classic ABC mapping

2026-08-19 11:42:59 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

ecp5: loosen tests

2026-09-17 15:43:54 +02:00

synth_efinix: remove classic ABC mapping

2026-08-19 11:42:59 +01:00

synth_fabulous: remove classic ABC mapping

2026-08-19 11:42:59 +01:00

tests: signorm fix

2026-09-17 15:43:55 +02:00

gowin: loosen tests

2026-09-17 15:43:55 +02:00

tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

intel_alm: loosen tests

2026-09-17 15:43:55 +02:00

synth_lattice: remove classic ABC mapping

2026-08-19 11:43:00 +01:00

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

Merge branch 'main' into nella/latch-toggle

2026-07-08 11:41:08 +02:00

nexus: loosen tests

2026-09-17 15:43:54 +02:00

Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7

2026-07-09 08:46:46 +00:00

xilinx_dsp: signorm compatibility

2026-09-17 15:43:54 +02:00

generate_mk.py

Move output redirect to one place

2026-04-16 11:00:44 +02:00