Emil J. Tywoniak 9d93aa275a tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

..

aiger

Move rename logic to abc_ops_reintegrate

2026-06-19 10:46:47 +01:00

alumacc

Code cleanup

2026-08-04 17:18:22 +02:00

arch

tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

arith_tree

arith_tree: add regression tests for truncating narrow chain links

2026-08-21 10:38:58 +02:00

asicworld

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

bind

Use generic testing on few more places

2026-04-16 11:00:44 +02:00

blif

Cleanup

2026-04-16 11:00:44 +02:00

bram

Revert "tests: use memory -bram-register in tests/bram"

2026-09-17 15:43:55 +02:00

bugpoint

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

check_mem

tests/check_mem: Drop unused init check

2026-05-30 11:06:11 +12:00

cxxrtl

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

errors

End of file fix

2026-06-23 07:23:41 +02:00

fmt

Cleanup

2026-04-16 11:00:44 +02:00

fsm

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

functional

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

hana

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

liberty

Move scl cache args to libcache, fix -disable.

2026-08-17 12:37:49 +02:00

lut

Adding test to demonstrate techmap failure with lut_cmp

2026-08-14 10:08:40 -06:00

memfile

Update CI scripts for CMake

2026-06-03 08:58:11 +00:00

memlib

tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

memories

Fix OOB read.

2026-08-07 14:29:14 +02:00

opt

opt_expr: ignore $input_port

2026-09-18 17:27:47 +02:00

opt_share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

peepopt

Converted some more

2026-04-16 11:00:44 +02:00

proc

tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

pyosys

End of file fix

2026-06-23 07:23:41 +02:00

realmath

Cleanup

2026-04-16 11:00:44 +02:00

rpc

Make out of tree build testing possible

2026-05-19 14:26:07 +02:00

rtlil

tests: fix rtlil roundtrip test

2026-09-17 14:13:57 +02:00

sat

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

sdc

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

select

select: alias wires don't count for cone depth

2026-09-15 12:00:03 +02:00

share

Did share, opt_share and fsm

2026-04-16 11:00:44 +02:00

sim

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

simple

End of file fix

2026-06-23 07:23:41 +02:00

simple_abc9

Convert autotest script wrapper

2026-04-16 11:00:44 +02:00

smv

End of file fix

2026-06-23 07:23:41 +02:00

sva

End of file fix

2026-06-23 07:23:41 +02:00

svinterfaces

Cleanup

2026-04-16 11:00:44 +02:00

svtypes

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

symfpu

Code cleanup

2026-08-04 17:18:22 +02:00

techmap

tests: signorm fix

2026-09-17 15:43:55 +02:00

tools

End of file fix

2026-06-23 07:23:41 +02:00

unit

opt_clean: rewrite with signorm

2026-09-18 17:29:41 +02:00

various

tests: ignore $input_port and $connect in cell counts

2026-09-18 17:37:03 +02:00

verific

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00

verilog

reset default_nettype on `resetall for the lexer

2026-08-16 14:26:21 -07:00

vloghtb

End of file fix

2026-06-23 07:23:41 +02:00

write_verilog

tests: Add mixed_upto write_verilog test

2026-06-19 11:20:01 +12:00

xprop

Update CI scripts for CMake

2026-06-03 08:58:11 +00:00

.gitignore

Save results, and create summary and report

2026-04-16 11:00:44 +02:00

common.mk

Add VERBOSE (and V) option to Makefiles

2026-06-15 14:48:11 +02:00

gen_tests_makefile.py

Fix OOB read.

2026-08-07 14:29:14 +02:00

Makefile

Adding test to demonstrate techmap failure with lut_cmp

2026-08-14 10:08:40 -06:00

pass-fuzzing.md

Remove trailing whitespaces

2026-06-23 07:24:59 +02:00