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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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0ce1cbcae7af1902b421ff0acd0e00a8e8ba9de8
yosys/frontends/verilog
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Miodrag Milanovic 7149b19f64 read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
..
.gitignore
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-08-11 13:34:10 +02:00
CMakeLists.txt
[core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration
2026-08-21 12:09:04 -07:00
const2ast.cc
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
preproc.cc
logger: add LogSourceLocation
2026-09-15 14:29:36 +02:00
preproc.h
reset default_nettype on `resetall for the lexer
2026-08-16 14:26:21 -07:00
verilog_error.cc
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
verilog_error.h
Use C++ stringf machinery in verilog_error
2025-09-12 06:21:56 +00:00
verilog_frontend.cc
reset default_nettype on `resetall for the lexer
2026-08-16 14:26:21 -07:00
verilog_frontend.h
Clean up diagnostics.
2026-07-31 10:31:44 +02:00
verilog_lexer.h
verilog_lexer: refactor
2025-08-11 13:34:10 +02:00
verilog_lexer.l
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
verilog_location.h
read_verilog logging to_src() - > to_loc()
2026-09-16 12:30:40 +02:00
verilog_parser.y
rtlil: remove dead verilog bindings
2026-08-31 22:13:01 +02:00
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