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18391 Commits

Author SHA1 Message Date
nataliakokoromyti f3c87610f5 verific: allow mixed SV/VHDL in -f files 2026-01-24 23:46:45 -08:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Robert O'Callahan 7d53d64a47 Make the call to `compare_signals()` easier to read. 
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
 2026-01-24 02:01:05 +00:00
Robert O'Callahan 2468b391bf Make `compare_signals` produce a total order. 
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
 2026-01-24 02:00:33 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella 0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan 4f53612725 Add `linux_perf` command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
Robert O'Callahan dcd7742d52 Avoid scanning entire module if there are no wires to remove 
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
 2026-01-23 01:38:20 +00:00
Robert O'Callahan e87bb65956 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
KrystalDelusion 98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages 
Document nesting packages as unsupported
 2026-01-23 07:16:22 +13:00
Akash Levy 5a6dffeecd Silimate mods to upstream opt_balance_tree pass 2026-01-21 23:34:34 -08:00
Akash Levy 4242d7022c
Merge branch 'YosysHQ:main' into main 2026-01-21 17:23:46 -08:00
Akash Levy 59fdd9105e
Merge pull request #95 from stanminlee/main 
Register annotation
 2026-01-21 17:23:35 -08:00
github-actions[bot] a6fc695522 Bump version 2026-01-22 00:28:34 +00:00
Stan Lee adab53eb96
Merge branch 'Silimate:main' into main 2026-01-21 16:12:32 -08:00
Akash Levy c49055cb4e
Remove persist-credentials from checkout steps 
Removed 'persist-credentials: false' from multiple checkout steps.
 2026-01-21 16:11:54 -08:00
Stan Lee a52689a1fa
Merge branch 'main' into main 2026-01-21 15:46:06 -08:00
Stan Lee 99cf75531f merge 2026-01-21 15:43:25 -08:00
Stan Lee f026cebaf6 address comments 2026-01-21 15:16:45 -08:00
Akash Levy 947139aca1 Remove opt_balance_tree from silimate (now in opt) 2026-01-21 15:15:21 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Stan Lee f14eb4a7bb only check reg cells 2026-01-21 15:13:55 -08:00
Stan Lee 269b70c0f9 compiles 2026-01-21 12:32:38 -08:00
Stan Lee 0018037c16 minor changes 2026-01-21 12:25:28 -08:00
Stan Lee e824c8e0d6 ready for review 2026-01-21 09:00:46 -08:00
Stan Lee 31e32af4a8 greptile 2026-01-21 08:54:43 -08:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Miodrag Milanović 2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy 
Avoid spurious copy in `IdStringCollector::trace_named()`
 2026-01-21 08:30:07 +01:00
Stan Lee d2e8f9b8a8 first round fixes 2026-01-20 21:45:13 -08:00
Robert O'Callahan 2c0448a81b Avoid spurious copy in `IdStringCollector::trace_named()` 2026-01-21 03:31:56 +00:00
github-actions[bot] 57ac113b7f Bump version 2026-01-21 00:27:51 +00:00
Stan Lee 29061d3051 leave no room for err 2026-01-20 15:55:05 -08:00
Stan Lee 45bd3f4515 change splitcells pass to remove some bracket from register names in blast mode 2026-01-20 15:50:43 -08:00
Stan Lee 60a81a2676 reg rename pass reads from vcd for original widths 2026-01-20 15:35:13 -08:00
Stan Lee a5106da733 line reduction 2026-01-20 11:56:57 -08:00
Stan Lee 0ea4bb8a2d comment 2026-01-20 11:55:54 -08:00
Stan Lee 80364c608e significantly cleaner 2026-01-20 11:29:56 -08:00
Gus Smith 9ed56ac72c Mimic pattern of how other tests build plugins 
Seems like using --build isn't supported in CI
 2026-01-20 10:44:47 -08:00
Gus Smith bd9dbea4ea Add -I 2026-01-20 10:07:44 -08:00
Gus Smith 0f6ef77775 Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
Gabriel Gouvine 979b673f20 ezsat: Fix handling of error codes 2026-01-20 07:54:50 -08:00
Gabriel Gouvine d2b6bd00b1 ezsat: Rename files and class for ezCmdlineSat 2026-01-20 07:54:50 -08:00
Gabriel Gouvine 6565bf3ebf ezsat: Fix build for emscripten/wasi 2026-01-20 07:54:50 -08:00
Gabriel Gouvine 12315c0d17 ezsat: Support for assumptions in Sat command 2026-01-20 07:54:49 -08:00
Gabriel Gouvine 9315f02c17 ezsat: New Sat class to call an external command 2026-01-20 07:54:49 -08:00
Miodrag Milanović bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017 
verific: add explicit System Verilog 2017 option
 2026-01-20 14:44:46 +01:00