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16708 Commits

Author SHA1 Message Date
abhinavputhran ec54c36850 dfflibmap: pass selection to dfflegalize dfflibmap was calling dfflegalize on the whole design regardless of the active selection, causing unselected modules to be modified. Fix by appending selected module names to the dfflegalize command. Fixes #5650 2026-03-06 15:13:04 -05:00
Emil J 04113eb95d
Merge pull request #5714 from likeamahoney/auto-proc-vars 
support automatic lifetime qualifier on procedural variables
 2026-03-03 17:31:37 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
likeamahoney e9442194f2 support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00
Miodrag Milanović 687a36af38
Merge pull request #5711 from YosysHQ/gowin_warning 
gowin: remove spurious warning
 2026-02-27 14:04:27 +01:00
Miodrag Milanovic 7f1f247c56 gowin: remove spurious warning 2026-02-27 13:12:32 +01:00
Miodrag Milanović 2dd71c3ba2
Merge pull request #5709 from YosysHQ/update_abc 
Update ABC as per 2026-02-27
 2026-02-27 08:32:34 +01:00
Miodrag Milanovic b3caec1a93 Update ABC as per 2026-02-27 2026-02-27 07:55:34 +01:00
nella 2c52546e2a Fix docs. 2026-02-25 16:42:05 +01:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Miodrag Milanović fd1ac58767
Merge pull request #5706 from YosysHQ/remove-flake-lock 
Remove already disabled CI job
 2026-02-25 11:15:33 +01:00
Miodrag Milanovic 31f7d0d92d Remove already disabled CI job 2026-02-25 10:36:46 +01:00
Miodrag Milanović 53d8eb43ff
Merge pull request #5702 from YosysHQ/verific_build_all 
Check verific configurations
 2026-02-23 09:41:59 +01:00
Miodrag Milanovic b51110a50b Build various Verific configurations 2026-02-23 09:01:55 +01:00
Krystine Sherwin fd311c5501 tests/arch/gowin: Add wr_en test 2026-02-22 09:00:37 +01:00
Krystine Sherwin 2386923b8f gowin: Fix bram ADA byte enables 2026-02-22 09:00:37 +01:00
Miodrag Milanović fb653c4181
Merge pull request #5700 from YosysHQ/wasi_speedup 
CI: WASI - Applying YoWASP changes to script
 2026-02-20 18:00:24 +01:00
Miodrag Milanovic 68e47ebcfe CI: WASI - Applying YoWASP changes to script 2026-02-20 15:23:45 +01:00
Miodrag Milanović 0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify 
abc9: verify post-mapping equivalence by default
 2026-02-20 13:41:11 +01:00
Krystine Sherwin 094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
Emil J 13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks 
aigerparse: add some bounds checks
 2026-02-20 11:53:49 +01:00
Emil J 74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Emil J 53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion 
modtools: fix database sanity
 2026-02-20 10:49:28 +01:00
Miodrag Milanović 679156d323
Merge pull request #5686 from YosysHQ/version_bump 
Automatic version bump
 2026-02-19 09:52:22 +01:00
Emil J. Tywoniak abc7563a35 modtools: add ModIndex unit test 2026-02-18 22:15:44 +01:00
Emil J. Tywoniak c75d80905a modtools: fix database sanity on wire name swap 2026-02-18 21:23:21 +01:00
Gus Smith 29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Miodrag Milanovic 5bb31485b7 Display repo and branch when applicable 2026-02-18 13:34:36 +01:00
Emil J. Tywoniak 62f19cb3a9 modtools: fix port_del db erase 2026-02-18 12:20:36 +01:00
Emil J 33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
nella 01e89a8f9e Remove cell mentions. 2026-02-18 09:29:35 +01:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
Emil J. Tywoniak 77f64de997 satgen: move report_missing_model here from equiv.h 2026-02-16 17:01:09 +01:00
Emil J. Tywoniak 81ea922512 sat: use the same cell import warnings as equiv 2026-02-16 16:54:26 +01:00
Miodrag Milanovic 63068f9b8f count relative to version tag, and ignore non existing 2026-02-16 16:44:33 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Miodrag Milanović ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Miodrag Milanovic 0090aa96b6 Remove version bump action 2026-02-13 14:22:33 +01:00
Miodrag Milanovic adf8b6b0d8 Add +post to version if from tarbal 2026-02-13 14:22:10 +01:00
Miodrag Milanovic c7d88ded94 Make version bump automatic 2026-02-13 14:21:41 +01:00
Chris Hathhorn 1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
github-actions[bot] e2f0c4d9a0 Bump version 2026-02-13 00:35:27 +00:00
Miodrag Milanovic bb7aa7d208 Cleanup of yml files 2026-02-12 14:56:45 +01:00
Miodrag Milanović e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic e5b3e9fc1f This one should run only vanilla-tests 2026-02-12 14:08:49 +01:00
Miodrag Milanovic c6e48f4bea These are tests from other Makefile 2026-02-12 14:06:08 +01:00
Miodrag Milanovic cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Maxim Kudinov 5b94a97fb3 gowin: synth_gowin: Add -nodsp option 2026-02-12 13:58:47 +03:00
Maxim Kudinov 542b29fa6a gowin: synth_gowin: Merge flatten label with coarse 2026-02-12 13:58:47 +03:00