mirror of https://github.com/YosysHQ/yosys.git
modtools: fix port_del db erase
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@ -94,8 +94,11 @@ struct ModIndex : public RTLIL::Monitor
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{
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for (int i = 0; i < GetSize(sig); i++) {
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RTLIL::SigBit bit = sigmap(sig[i]);
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if (bit.wire)
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if (bit.wire) {
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database[bit].ports.erase(PortInfo(cell, port, i));
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if (!database[bit].is_input && !database[bit].is_output && database[bit].ports.empty())
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database.erase(bit);
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}
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}
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}
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