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4916 Commits

Author SHA1 Message Date
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00
Gus Smith f062a0c8d6 Typo 2026-02-06 17:26:08 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Robert O'Callahan 7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE 
(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
 2026-02-04 17:19:10 +13:00
Emil J. Tywoniak ed53ff2f49 equiv_simple, equiv_induct: fix config 2026-02-03 18:37:39 +01:00
Emil J. Tywoniak 8d1c1faf82 equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 8e73e2a306 sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 000be270ca equiv_simple, equiv_induct: refactor 2026-02-03 17:54:46 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Robert O'Callahan 9c56c93632 Add missing newlines to some 'log_error's 2026-01-30 01:52:19 +00:00
Robert O'Callahan 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal 2026-01-30 01:52:19 +00:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Robert O'Callahan 139c38ecfa Dump module details when design_equal fails 2026-01-28 18:32:12 +00:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 6a6e5f0f54 linux_perf: only include unistd on Linux 2026-01-28 03:44:33 -08:00
Natalia fc2b7c317f linux_perf: include unistd for POSIX I/O 2026-01-28 03:14:20 -08:00
Emil J 75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help 
linux_perf: mark internal, fix help formatting
 2026-01-28 11:06:08 +01:00
Krystine Sherwin 8ed7ac04d8
linux_perf.cc: Fix overlength codeblock 2026-01-28 08:17:56 +13:00
Krystine Sherwin 4031310ebb
linux_perf.cc: Use formatted_help 
Gets the codeblock formatting better.

Also fold the on|off into a single usage.
 2026-01-28 08:10:31 +13:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J. Tywoniak ef3b2b0380 linux_perf: mark internal, fix help formatting 2026-01-26 22:59:20 +01:00
nella 9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella 5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
Emil J 29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl 
Add `linux_perf` command to turn Linux perf recording on and off.
 2026-01-26 19:32:55 +01:00
nella 8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
Emil J 673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Robert O'Callahan 7d53d64a47 Make the call to `compare_signals()` easier to read. 
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
 2026-01-24 02:01:05 +00:00
Robert O'Callahan 2468b391bf Make `compare_signals` produce a total order. 
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
 2026-01-24 02:00:33 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella 0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan 4f53612725 Add `linux_perf` command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
Robert O'Callahan e87bb65956 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Lofty 5a9d73369a abc9: verify post-mapping equivalence by default 2026-01-20 09:58:35 +00:00
Martin Povišer 90673cb0a2 techmap: Use `-icells` mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
nataliakokoromyti 8a596f330a Update lut2mux.cc 2026-01-13 15:02:17 -08:00
nataliakokoromyti 40f9e235de
Update lut2mux.cc 2026-01-13 14:45:46 -08:00
nataliakokoromyti 6a93a94d9f
fix line 2026-01-13 14:44:51 -08:00
nataliakokoromyti c305c426eb
restore extra_args 2026-01-13 14:43:52 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic 2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan 37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
KrystalDelusion cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 5c630a366d
Merge pull request #5555 from rocallahan/defer-redirects 
Defer redirecting cell outputs when merging cells in `opt_merge` untill after we've done a full pass over the cells.
 2026-01-06 18:48:16 +01:00
Robert O'Callahan 042ec1cf60 Defer redirecting cell outputs when merging cells in `opt_merge` until after we've done a full pass over the cells. 
This avoids changing `assign_map` and `initvals`, which are inputs to the hash function for `known_cells`,
while `known_cells` exists. Changing the hash function for a hashtable while it exists leads to
confusing behavior. That also means the exact behavior of `opt_merge` cannot be reproduced by a
parallel implementation.
 2026-01-06 16:21:48 +00:00
Natalia 11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
Miodrag Milanović aa9991d3ee
Merge pull request #5571 from YosysHQ/micko/warning 
remove unused variable
 2025-12-23 16:32:10 +01:00
Miodrag Milanovic 4bc4e4eb41 remove unused variable 2025-12-23 15:47:35 +01:00
Natalia 721b504479 lut2mux: add -word option and test 2025-12-23 05:57:40 -08:00
Miodrag Milanović 09f9e0e8d1
Merge pull request #5568 from rocallahan/abc-spawn-errno 
Print `errno` to help diagnose failure to spawn ABC
 2025-12-23 08:09:14 +01:00
Robert O'Callahan 0e61f57458 Print errno to help diagnose failure to spawn ABC 2025-12-22 21:58:15 +00:00
N. Engelhardt d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties 2025-12-22 16:54:43 +01:00
Robert O'Callahan 48cdb499f2 Remove `IdString::id_string()`. 
This was needed for the short time when `ID()` could return a value of `StaticIdString`.
That is no longer a problem.
 2025-12-22 01:57:30 +00:00
Robert O'Callahan 46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
Robert O'Callahan 914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Krystine Sherwin 5b317ee03c
sim.cc: Check eval err 
Some cells (e.g. $macc_v2) are marked evaluable, but will raise an abort if called with `CellTypes::eval()`.
Instead of falling through to the abort, we can pass a pointer to a boolean to check for errors.
Use said check to catch `CellTypes::eval()` errors and treat them as unevaluable but otherwise continue.
Reflows the series of if checks into `if ... else if ... else` so that we can check for errors and set state in one place.
 2025-12-15 12:08:07 +13:00
Krystine Sherwin 9d3d8bf502
Switch posix_spawn to posix_spawnp 2025-12-15 09:40:04 +13:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Robert O'Callahan 638e904f91 Remove cover() coverage tracking 2025-12-04 16:27:13 +01:00
Krystine Sherwin 9ec361beab
test_cell.cc: Generate .aag for all compatible cells 
Skips (with warning) on cells that didn't convert to avoid `write_aiger` from raising an error.
 2025-12-02 14:03:36 +13:00
Emil J 9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops 
read_liberty: support loopy retention cells
 2025-12-01 22:50:20 +01:00
Emil J 510f9ef63d
Merge pull request #5499 from mikesinouye/abc_new 
Enable abc_new pass when not in NDEBUG
 2025-11-24 16:57:29 +01:00
Emil J. Tywoniak e8cbc92462 abc_new: sorted -> is_sorted 2025-11-24 11:46:09 +01:00
Robert O'Callahan 53614a37a1 Use `Tcl_Size` instead of `int` to fix build errors 
Fixes these build errors I'm getting locally with `tcl-devel-9.0.0-7.fc42.x86_64`.
I guess Tcl 9 broke this.

```
passes/cmds/sdc/sdc.cc:438:6: error: no matching function for call to 'Tcl_ListObjLength'
  438 |         if (Tcl_ListObjLength(interp, listObj, &listLength) == TCL_OK) {
      |             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
passes/cmds/sdc/sdc.cc:446:8: error: no matching function for call to 'Tcl_ListObjLength'
  446 |                         if (Tcl_ListObjLength(interp, subListObj, &subListLength) == TCL_OK) {
      |                             ^~~~~~~~~~~~~~~~~
/usr/include/tclDecls.h:1788:13: note: candidate function not viable: no known conversion from 'int *' to 'Tcl_Size *' (aka 'long *') for 3rd argument
 1788 | EXTERN int              Tcl_ListObjLength(Tcl_Interp *interp,
      |                         ^
 1789 |                                 Tcl_Obj *listPtr, Tcl_Size *lengthPtr);
      |                                                   ~~~~~~~~~~~~~~~~~~~
```
 2025-11-24 18:46:56 +13:00
Mike Inouye 615e338acd
Fix abc_new pass when not in NDEBUG 2025-11-21 14:10:05 -08:00
Robert O'Callahan e33ca17388 Force a newline to appear before YOSYS_ABC_DONE 2025-11-21 03:50:07 +00:00
Emil J. Tywoniak b3112bf025 filterlib: prefer using precedence over unsynthesizable verilog 2025-11-21 00:43:54 +01:00
Emil J. Tywoniak 6eb9e823e0 sdc: use Tcl memory management functionality 2025-11-20 00:21:15 +01:00
Emil J 2eff366e8c
Merge branch 'main' into emil/sdc_expand 2025-11-19 16:29:37 +01:00
Emil J. Tywoniak 920f4793fb sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 229123eb87 sdc: disable without YOSYS_ENABLE_TCL 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 033a2d5a67 sdc: remove vestigial code for tracked constraint followup work 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak f56e121ddb sdc: add help 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 650392d4ec sdc: specialize stubs for the call graph 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 224ed524fa sdc: move to directory 2025-11-19 15:26:01 +01:00
Emil J. Tywoniak 94dd248dfb sdc: graph mode only 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 8a54e51300 sdc: add -keep_hierarchy 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak d4228efae8 sdc: keep_hiearchy 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 075237f73b sdc: refactor more 2025-11-19 15:25:24 +01:00
Emil Jiří Tywoniak 48ff9d4950 sdc: refactor find_matching 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak ae1235210d sdc: functional graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c6491629d8 sdc: start graph 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 24a6412ea8 sdc: bit selections 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 21c68e0022 sdc: unknown handler experiment 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 420a083d9b sdc: simple mode, remove per-tool stubs 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 834125a076 sdc: return resolved patterns 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak dc48ceadd9 sdc: collect strictly matching objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 9a3c7f70ad sdc: stubs SDC commands supported by OpenSTA 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c26aa3186d sdc: collect design objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c1c6ec1266 sdc: stubs SDC commands supported by Vivado 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak 5a798b64ef sdc: separate out 2025-11-19 15:25:22 +01:00
Emil J. Tywoniak 9a5465bc83 icell_liberty: simplify 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak cee3d0b598 icell_liberty: refactor and add help 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak e4e32d7966 icell_liberty: flop harder 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak c2c9506f4f icell_liberty: flops 2025-11-19 15:20:50 +01:00
Emil J. Tywoniak b3ead7e47d icell_liberty: start 2025-11-19 15:20:50 +01:00
Miodrag Milanović 4bfdc62f65
Merge pull request #5472 from Anhijkt/arst-fsm-handling 
fsm_detect: add adff detection
 2025-11-14 13:47:08 +01:00
Robert O'Callahan 8c2984dc5f Fix AbcModuleState::remap_name() to avoid calling IdString::c_str() 2025-11-12 11:52:04 +01:00
Robert O'Callahan 325b27f43a Avoid calling IdString::c_str() in opt_clean 2025-11-12 11:52:04 +01:00
Robert O'Callahan 54bde15329 Implement IdString garbage collection instead of refcounting. 2025-11-12 11:52:04 +01:00
Emil J. Tywoniak 967e91aa73 libparse: fix parsing and memory safety of quoted values 2025-11-11 13:44:50 +01:00
Emil J 365c6753c4
Merge pull request #5453 from rocallahan/sigspec-onechunk 
Make `SigSpec` const methods multithreading-compatible
 2025-11-10 17:48:42 +01:00
Robert O'Callahan 3f7af10eda Make SigSpec::chunks() return an object that can be iterated over without packing the SigSpec 2025-11-07 15:54:54 +00:00
KrystalDelusion 24b69cabaa
Merge pull request #5422 from YosysHQ/krys/SVI_support 
Catch partial support of SVI
 2025-11-07 11:16:07 +13:00
Anhijkt 7d10a72490 fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
Emil J a16fc9b4f3
Merge pull request #5467 from YosysHQ/emil/liberty-unquoted-expressions 
libparse: support unquoted expressions
 2025-11-06 19:45:17 +01:00
Emil J. Tywoniak fdcc4c1507 libparse: remove leftover comments 2025-11-06 13:30:09 +01:00
Emil J a2aeef6c96
Merge pull request #5461 from rocallahan/reset-abc-config 
Fix regression in configuring ABC techmapping
 2025-11-06 11:58:04 +01:00
Robert O'Callahan 0f770285f3 Move global ABC configuration variables into AbcConfig and initialize them properly 2025-11-05 13:56:04 +00:00
Emil J. Tywoniak 90553267b0 libparse: fix quoting and negedge in filterlib -verilogsim 2025-11-05 14:13:58 +01:00
Emil J. Tywoniak 504b668ea6 libparse: fix verilogsim negedge 2025-11-05 13:49:05 +01:00
Emil J. Tywoniak bf29f6dc11 libparse: tolerate closing quotes in expression parsing 2025-11-05 13:06:09 +01:00
Emil J. Tywoniak 4fac7a1b20 libparse: fix space before closing paren in expressions 2025-11-05 13:05:56 +01:00
Emil J. Tywoniak 547e254a9b libparse: parse expressions in filterlib 2025-11-05 13:05:56 +01:00
Emil J. Tywoniak 66d8fc5c28 libparse: quirk-compatibility for unquoted boolean expression strings 2025-11-05 11:00:25 +01:00
Martin Povišer 5fa7feccd3 timeest: Add top ports launching/sampling 2025-11-03 14:21:28 +01:00
Emil J. Tywoniak b2fe335b2d dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity 2025-10-28 13:56:28 +01:00
Miodrag Milanović 2613c1c0a9
Merge pull request #5438 from cr1901/posix-bugpoint 
Add sys/wait.h header to bugpoint to bring in constants.
 2025-10-22 12:40:26 +02:00
William D. Jones 311a2739f6 Add sys/wait.h header to bugpoint to bring in constants. 2025-10-20 19:50:18 -04:00
Jannis Harder 6a0ee6e4fb Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00