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1738 Commits

Author SHA1 Message Date
Gus Smith c06ed12718
Merge 8a282b3c17 into 413169663d 2026-04-13 15:51:34 +02:00
Emil J b485173428
Merge pull request #5792 from YosysHQ/emil/toposort-stability 
toposort: avoid run to run variance caused by pointer sensitivity
 2026-04-08 08:51:47 +00:00
Emil J. Tywoniak cd49dc7be8 cxxrtl: stable TopoSort 2026-04-06 15:09:52 +02:00
Lofty b55fd6718b write_xaiger2: fix indentation 2026-04-02 10:47:08 +01:00
Lofty 568a31c83a write_xaiger2: fix function argument evaluation order 2026-03-31 10:40:58 +01:00
Gus Smith 10b87cee43 Add `signed` keyword in write_verilog 2026-03-23 15:20:42 -07:00
Catherine 18d94fe9a4
Merge pull request #5740 from kivikakk/push-utvloulmsuqy 
cxxrtl: Suppress another un/signed comparison warning!
 2026-03-11 10:27:27 +00:00
Asherah Connor 5c74446e57 cxxrtl: Suppress another un/signed comparison warning! 2026-03-11 20:50:09 +11:00
Asherah Connor c5c104f560 cxxrtl: Suppress un/signed comparison warning; this is positive 2026-03-11 18:35:48 +11:00
nella 16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella cae54a4c7b Aiger use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 7a5c303ccd backends: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 665b6eeb4a aiger2: add TODO 2026-03-04 12:22:14 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith 1ede98797f Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 9ad7aed4a5 Update backends/verilog/verilog_backend.cc 
Co-authored-by: Marcelina Kościelnicka <236399+mwkmwkmwk@users.noreply.github.com>
 2026-02-11 08:10:57 -08:00
Gus Smith 12ace45b89 Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00
kamay e0077b188d Add gatesi_mode in BLIF format 2026-01-14 21:41:56 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Gus Smith 4d237bdd92 Deliver more helpful error messages 2026-01-06 16:19:54 -08:00
Krystine Sherwin fcb8695261
write_verilog: Skip empty switches 2026-01-07 13:09:49 +13:00
Robert O'Callahan 46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
Emil J 46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input 
aiger2: fix empty cell input
 2025-12-04 16:47:53 +01:00
Gus Smith dd65dd610d Fixes 2025-12-02 11:17:21 -08:00
Emil J. Tywoniak b2270ae1c8 aiger2: fix case where submodule cell input port has empty SigSpec 2025-12-01 19:40:58 +01:00
Emil J. Tywoniak cebb80250c aiger2: formatting 2025-12-01 19:40:17 +01:00
Gus Smith ade6379345 Explicitly store whether to use association lists 
Instead of checking for the presence of helper names each time we need to
determine whether to use association lists, explicitly store a boolean flag
indicating whether association list helpers are being used.
 2025-11-29 15:24:56 -08:00
Gus Smith ddcd93024f Capture error case more correctly 2025-11-29 15:20:37 -08:00
Gus Smith ded7c9cb03 More formatting undos' 2025-11-29 14:59:04 -08:00
Gus Smith 9909049d2a Undo formatting changes 2025-11-29 14:55:55 -08:00
Gus Smith 6fe35fa46c Merge remote-tracking branch 'origin/main' into gussmith23-rosette-backend-updates 2025-11-29 14:20:36 -08:00
Robert O'Callahan b870693393 Fix reset_auto_counter_id to correctly detect _NNN_ patterns 
This fixes a regression caused by commit c4c389fdd7.
 2025-11-17 09:21:59 +00:00
Robert O'Callahan c4c389fdd7 Fix verilog backend to avoid IdString::c_str() 2025-11-12 11:52:04 +01:00
KrystalDelusion 529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params 
Handle unsized params
 2025-11-12 07:14:44 +13:00
Robert O'Callahan 92ea557979 Build a temporary SigChunk list in the iterator in the cases where that's needed 2025-11-07 15:54:55 +00:00
Krystine Sherwin 7302bf9a66
Add CONST_FLAG_UNSIZED 
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
 2025-11-07 17:45:07 +13:00
KrystalDelusion 52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor 
Refactor getting dirs and filenames from paths to files
 2025-11-05 09:12:54 +13:00
Emil J. Tywoniak 5cfe6a9c1e reduce OS ifdefs, refactor getting dirs and filenames from paths to files 2025-10-14 15:46:17 +02:00
Krystine Sherwin 1a0b5d8ea7 write_btor: Include `$assert` and `$assume` cells in -ywmap output 2025-10-09 14:50:36 +02:00
Jannis Harder 90669ab4eb aiger2: Only fail for reachable undirected bufnorm helper cells 
The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.

Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.

With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
 2025-09-29 08:21:28 +02:00
Robert O'Callahan 1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Emil J a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 
write_rtlil: don't sort
 2025-09-22 11:14:39 +02:00
Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
 2025-09-17 14:01:09 +02:00
Jannis Harder 47b3ee8c8b write_aiger2: Ignore the $input_port cell during indexing. 
The $input_port cell is added by the bufnorm code to simplify handling
of input ports for new code that uses bufnorm, but the aiger2 backend
does already handle input ports separately, so we just ignore those.
 2025-09-17 13:56:46 +02:00
Jannis Harder 4918f37be3 write_aiger2: Treat inout ports as output ports 
With the previous bufnorm implementation inout ports were not supported
at all, so this didn't matter, but with the new bufnorm implementation
they need to be treated as output ports.
 2025-09-17 13:56:46 +02:00
Jannis Harder 6466b15367
Merge pull request #5351 from jix/xaiger_ponum_fix 
write_xaiger2: Fix output port mapping when opaque boxes are present
 2025-09-17 13:56:21 +02:00
Jannis Harder 2d81726459 write_xaiger2: Fix output port mapping when opaque boxes are present 2025-09-17 13:10:04 +02:00