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Merge 8a282b3c17 into 413169663d

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Gus Smith 2026-04-13 15:51:34 +02:00 committed by GitHub
parent 413169663d 8a282b3c17
commit c06ed12718
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3 changed files with 40 additions and 5 deletions
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11
backends/verilog/verilog_backend.cc
View File

@ -456,21 +456,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
if (wire->attributes.count(ID::single_bit_vector))
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
}
std::string sign = wire->is_signed ? " signed" : "";
if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name));
if (!wire->port_input && wire->port_output)
f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name));
if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name));
if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent, range, id(wire->name));
f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name));
if (wire->attributes.count(ID::init)) {
f << stringf(" = ");
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else
f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name));
f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name));
#endif
}

16
tests/verilog/issue4402.ys Normal file
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@ -0,0 +1,16 @@
# Issue #4402: read_verilog doesn't respect signed keyword
#
# write_verilog was not emitting the signed keyword for port declarations.
! mkdir -p temp
read_verilog <<EOT
module mod (output k, input signed [5:0] wire0);
assign k = (wire0 <= 0);
endmodule
EOT
hierarchy -top mod
write_verilog temp/issue4402_roundtrip.v
# The output port declaration must include the signed keyword.
! grep -q "input signed" temp/issue4402_roundtrip.v

18
tests/verilog/issue5745.ys Normal file
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@ -0,0 +1,18 @@
# Issue #5745: chparam values are unsigned when using read_verilog frontend
#
# When chparam overrides a parameter value, the signed attribute is lost,
# causing signed comparisons to silently use unsigned logic.
#
# m = -32 (signed 9-bit), p2 = 11. Correct signed semantics: -32 < 11, so k = 1.
# Bug: chparam strips the signed attribute from p2. The $lt cell gets A_SIGNED=0,
# B_SIGNED=0, so the comparison treats m as unsigned (480 > 11), giving k = 0.
read_verilog <<EOT
module mod #(parameter p2=11) (output k);
wire signed [8:0] m = -32;
assign k = m < p2;
endmodule
EOT
chparam -set p2 11
hierarchy -top mod
sat -prove k 1 -verify