mirror of https://github.com/YosysHQ/yosys.git
write_aiger2: Ignore the $input_port cell during indexing.
The $input_port cell is added by the bufnorm code to simplify handling of input ports for new code that uses bufnorm, but the aiger2 backend does already handle input ports separately, so we just ignore those.
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@ -91,7 +91,7 @@ struct Index {
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int pos = index_wires(info, m);
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for (auto cell : m->cells()) {
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if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3)))
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if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port)))
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continue;
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Module *submodule = m->design->module(cell->type);
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