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Author SHA1 Message Date
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
Akash Levy 5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
Natalia 61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia 7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Akash Levy 5993d2fec8 Remove annoying test case 2026-01-28 19:18:06 -08:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia 8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia 74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
Akash Levy 9baad1beb7 Smallfix 2 2026-01-27 15:03:10 -08:00
Akash Levy 89ce04a221 Fix abc bug 2026-01-27 14:01:38 -08:00
Akash Levy 26f5ff3d74 Merge from upstream 2026-01-26 22:16:11 -08:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J 5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
nella a3c9716f18 OptDff fix unit tests. 2026-01-26 22:35:25 +01:00
Emil J 673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Akash Levy 947139aca1 Remove opt_balance_tree from silimate (now in opt) 2026-01-21 15:15:21 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Gus Smith 491276983e Add test 2026-01-19 18:34:55 -08:00
Krystine Sherwin 0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Natalia cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Akash Levy ef98c62bf2 Merge 2026-01-14 18:34:16 -08:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
Emil J. Tywoniak ddf3c6c8b7 blif: add -gatesi test 2026-01-14 21:41:56 +01:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Akash Levy a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Akash Levy 58192ad8a6
Merge branch 'YosysHQ:main' into main 2026-01-12 22:52:03 -08:00