luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
17,579 Commits 137 Branches 69 Tags 54 MiB
Commit Graph

17579 Commits

Author SHA1 Message Date
nella 8ab880b98b
Merge 88da4a644b into 4821ed17b4 2026-07-29 09:49:21 +02:00
nella 4821ed17b4
Merge pull request #5929 from YosysHQ/nella/fuse-2 
Add register absorption for MULT* for Nexus (fix #5917).
 2026-07-29 00:29:16 +00:00
nella c1377426c9
Merge branch 'main' into nella/fuse-2 2026-07-29 01:41:37 +02:00
Emil J 07a615a283
Merge pull request #6068 from YosysHQ/emil/aigmap-remove-unused-cache 
aigmap: remove unused and_cache
 2026-07-27 20:40:51 +00:00
Emil J. Tywoniak 6585661740 aigmap: remove unused and_cache 2026-07-27 16:50:38 +02:00
Miodrag Milanović 2c28591b8e
Merge pull request #6067 from donn/force_static_ffi 
wheels: force static libffi in build
 2026-07-27 13:11:49 +00:00
nella 88da4a644b Budget SAT effort via shared SatEffortBudget. 2026-07-27 14:52:54 +02:00
nella 3ac8daafd1 Add reusable SatEffortBudget helper to qcsat. 2026-07-27 14:52:54 +02:00
Mohamed Gaber a216efad1c
wheels: force static libffi in build 
- only build static libffi
- improve resilience of cibw environment variables
 2026-07-27 15:40:23 +03:00
Emil J 5d2fbf8187
Merge pull request #5961 from YosysHQ/emil/opt_muxtree-fix-reconvergence 
opt_muxtree: fix reconvergence
 2026-07-27 09:08:13 +00:00
nella 5489a9adde Add SAT effort test. 2026-07-24 13:31:12 +02:00
nella a2b76556f3 Add help message + cleanup. 2026-07-24 13:31:12 +02:00
nella 7bdcc97aed Implement constbit gather. 2026-07-24 13:31:12 +02:00
nella 0bf4afc023 eqbits drop_all. 2026-07-24 13:31:12 +02:00
nella 0a6ff36e30 Test solve_budgeted. 2026-07-24 13:31:12 +02:00
nella 143975bd66 ezsat add propagation budget api. 2026-07-24 13:31:12 +02:00
nella 511017acc1
Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
nella 526ab7aab3 Use Nexus DSP pipelined registers. 2026-07-24 12:10:07 +02:00
nella 5e59deecc3 Fix test desc. 2026-07-24 12:07:10 +02:00
nella 7defa51862
Merge pull request #6007 from YosysHQ/nella/fix-shift-fold 
Fix wide shift count folded as truncated/signed negative count
 2026-07-24 08:17:11 +00:00
Krystine Sherwin 29a6295d7c
tests/opt: Fix comments 2026-07-23 14:59:12 +12:00
Lofty 30fe16c7f1
Merge pull request #6061 from YosysHQ/lofty/remove-flowmap 
flowmap: remove
 2026-07-22 13:57:19 +00:00
Miodrag Milanović bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only 
Add dependencies to gtests
 2026-07-22 13:39:05 +00:00
Miodrag Milanovic 5574994453 Add dependencies to gtests 2026-07-22 15:03:12 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
Lofty f9023e92b4
Merge pull request #6059 from drewbabel/fix-xilinx-srl-fdre-enable 
xilinx_srl: keep the clock enable on FDRE shift registers
 2026-07-22 10:33:29 +00:00
Lofty b914a7802e
Merge pull request #5782 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast (again)
 2026-07-21 09:26:10 +00:00
Lofty 45e1de36b4 abc: remove -fast (again) 2026-07-21 09:50:14 +01:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Miodrag Milanović e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu 
Add `symfpu` pass
 2026-07-20 10:20:23 +00:00
Miodrag Milanovic cfd80cb48e Update constids to fix leaks 2026-07-20 11:53:55 +02:00
Miodrag Milanovic a7cfabd405 Fix gcc compile errors 2026-07-20 10:29:41 +02:00
Miodrag Milanović 3ce3196265
Merge pull request #6056 from YosysHQ/mmicko/ci_skip_update 
CI: back to using official action
 2026-07-20 07:08:47 +00:00
Miodrag Milanovic 60403f35ca CI: back to using official action 2026-07-20 08:23:37 +02:00
Emil J 5f29546d80
Merge pull request #6050 from YosysHQ/emil/autoname-rewrite 
autoname: rewrite
 2026-07-19 22:10:02 +00:00
Krystine Sherwin c2237447bf
symfpu: Drop libs/ from symfpu includes 2026-07-20 09:58:04 +12:00
myrtle a0fbe6e133
Merge pull request #6054 from YosysHQ/gatecat/nexus-radiant-fix 
nexus: Fix Radiant netlist compatibility
 2026-07-19 13:22:46 +00:00
gatecat 15c54ae15e nexus: Fix Radiant netlist compatibility 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-07-19 12:44:40 +02:00
Catherine 6f7123d1d2
Merge pull request #6053 from whitequark/fix-libffi-detection 
Fix DPI-C support broken in v0.67
 2026-07-18 14:19:32 +00:00
Catherine 21aa69f448 Fix DPI-C support broken in v0.67. 
Fixes #6052.
 2026-07-17 22:21:59 +00:00
Emil J. Tywoniak 8565451ef9 autoname: selection determines what gets renamed, not the name it gets renamed to 2026-07-17 22:48:46 +02:00
Emil J. Tywoniak fb0bb160ad autoname: rewrite 2026-07-17 12:02:43 +02:00
Lofty 45ea2b8d6c
Merge pull request #6047 from olby/mul2dsp-commute-first 
mul2dsp: normalize operand order before min-width checks
 2026-07-15 15:47:08 +00:00
Johan Olby 63457de80e
mul2dsp: normalize operand order 
Move the operand commute that puts the wider operand on A ahead of the
min-width checks. Checking the min-widths first made an asymmetric rule
(DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the
wider operand on A; a product in the other order was rejected before the
normalization.
 2026-07-15 16:21:07 +02:00
Miodrag Milanović 9914b6fa25
Merge pull request #6044 from YosysHQ/mmicko/codeql 
codeql: do not generate reports for 3rd party code
 2026-07-15 07:12:44 +00:00
Miodrag Milanovic 6fa6849734 codeql: do not generate reports for 3rd party code 2026-07-15 08:54:10 +02:00
Miodrag Milanović 0135a61db3
Merge pull request #6043 from YosysHQ/mmicko/sv-elab 
Update sv-elab to 3dddccd
 2026-07-15 06:43:02 +00:00
Miodrag Milanovic eb3a15cd8c Update sv-elab to 3dddccd 2026-07-15 08:24:46 +02:00
Krystine Sherwin 9dd5c3a6a4
symfpu: Run pre-commit 2026-07-15 14:56:11 +12:00
Krystine Sherwin 6730b3ec54
libs/symfpu: Fixup submodule 2026-07-15 14:52:53 +12:00