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16924 Commits

Author SHA1 Message Date
nella 897306d040 Clang-Format CSA tree. 2026-04-07 18:58:31 +02:00
nella 44f35c82c7 Consolidate Wallace from booth and CSA. 2026-04-07 18:58:31 +02:00
nella 07566ceec5 Invert. 2026-04-07 18:58:31 +02:00
nella d01929c668 Clarify. 2026-04-07 18:58:31 +02:00
Emil J. Tywoniak 7380dc6952 csa_tree: move to techmap 2026-04-07 18:58:31 +02:00
Emil J. Tywoniak fa93400dec csa_tree: refactor 2026-04-07 18:58:31 +02:00
nella 7761bf1d77 Replace utf arrow with ascii arrow. 2026-04-07 18:58:31 +02:00
nella 7c8875d7a2 Cleaned up CSA tests. 2026-04-07 18:58:31 +02:00
nella 15644a354a rm misc comments. 2026-04-07 18:58:31 +02:00
nella b6628dfded Move csa after alumacc. 2026-04-07 18:58:31 +02:00
nella 551222a5a7 CSA add alumacc related tests. 2026-04-07 18:58:31 +02:00
nella 851cf7616b CSA add support for macc and alu cells. 2026-04-07 18:58:31 +02:00
nella cd55efa4f4 Consolidate csa tests. 2026-04-07 18:58:31 +02:00
nella 33f8e1b885 Tighten csa tests. 2026-04-07 18:58:31 +02:00
nella a4583ca57c Add csa to synth. 2026-04-07 18:58:31 +02:00
nella 72e2dc4fb3 Add more robsutness tests. 2026-04-07 18:58:31 +02:00
nella d5c8b4a913 Add chain tests and tighten synthesis assertions for csa. 2026-04-07 18:58:31 +02:00
nella 09d62a7fcc Add sub chain support for csa trees. 2026-04-07 18:58:31 +02:00
nella ecbbad0930 Edge case tests. 2026-04-07 18:58:31 +02:00
nella 56d912d742 Add csa synth tests. 2026-04-07 18:58:31 +02:00
nella e4cf7a39aa Add structural tests for csa_tree. 2026-04-07 18:58:31 +02:00
nella d32377061e better balancing. 2026-04-07 18:58:31 +02:00
nella 5eab50d0b2 impl csa tree. 2026-04-07 18:58:31 +02:00
Lofty a96cf8cc2b
Merge pull request #5789 from YosysHQ/lofty/abc-refactor-3 
aig-related cleanup [sc-269]
 2026-04-07 09:05:18 +00:00
Miodrag Milanović 37ca545b65
Merge pull request #5791 from YosysHQ/ci_macos 
Enable macOS builds
 2026-04-03 06:54:30 +00:00
Miodrag Milanovic d58e0447c7 Enable macOS builds 2026-04-03 07:59:00 +02:00
Lofty b55fd6718b write_xaiger2: fix indentation 2026-04-02 10:47:08 +01:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
Emil J ecaaea8734
Merge pull request #5786 from YosysHQ/gus/muxpack-wide-y-test 
Regression test for #5765
 2026-03-31 12:47:08 +02:00
Lofty 568a31c83a write_xaiger2: fix function argument evaluation order 2026-03-31 10:40:58 +01:00
Lofty 162eeea29a cellaigs: remove some dead code 2026-03-31 09:37:18 +01:00
Lofty 240439bdb0
Merge pull request #5781 from YosysHQ/update_abc 
Update ABC as per 2026-03-27
 2026-03-30 16:37:29 +00:00
Lofty 903695892a
Merge pull request #5784 from YosysHQ/lofty/abc-changelog 
changelog: update for abc changes
 2026-03-30 16:36:08 +00:00
Gus Smith 6a5fea1b27 Regression test for #5765 2026-03-30 08:59:28 -07:00
Lofty 0f87fd8ef6 changelog: update for abc changes 2026-03-30 15:24:07 +01:00
Miodrag Milanovic 417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanovic 23cfeabfe1 Update ABC as per 2026-03-27 2026-03-30 15:23:27 +01:00
Miodrag Milanović 74fef31bf2
Merge pull request #5773 from rocallahan/num-active-workers 
Prevent race on `num_active_worker_threads_`.
 2026-03-27 19:23:30 +00:00
Miodrag Milanović 18bcd0b499
Merge pull request #5785 from YosysHQ/fix_ci_temp 
CI: temporary disable macos for testing
 2026-03-27 17:34:18 +00:00
Miodrag Milanovic d37b02af03 CI: temporary disable macos for testing 2026-03-27 17:46:14 +01:00
Miodrag Milanović ebfe5b2c06
Merge pull request #5774 from Silimate/atondapu/sim-cache-sigmap 
sim: cache sigmap in register_output_step_values
 2026-03-25 06:40:01 +00:00
tondapusili 5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Robert O'Callahan 290fb0556d Prevent race on `num_active_worker_threads_`. 
The core issue here is that we need to ensure `num_active_worker_threads_`
is read before incrementing `done_workers`. See the comments
added in this PR to explain why, and why the resulting code is
race-free.
 2026-03-24 22:20:18 +00:00
Miodrag Milanović 66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00
Miodrag Milanović cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
Emil J 7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init 
genrtlil: fast memory initialization
 2026-03-23 10:21:21 +00:00
tondapusili 69219e6be0 sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
Miodrag Milanović 5fd39ff3e1
Merge pull request #5766 from YosysHQ/upgrade_ci 
Upgrade CI actions
 2026-03-19 18:06:50 +00:00
Emil J dc77140275
Merge pull request #5731 from YosysHQ/nella/wall-clock 
Implement wall clock time measurement
 2026-03-19 16:21:26 +00:00