mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #5789 from YosysHQ/lofty/abc-refactor-3
aig-related cleanup [sc-269]
This commit is contained in:
Lofty
GitHub
commit
a96cf8cc2b
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@ -177,6 +177,8 @@ struct Index {
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if (!strashing) {
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return (static_cast<Writer*>(this))->emit_gate(a, b);
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} else {
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// AigMaker::node2index
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if (a < b) std::swap(a, b);
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auto pair = std::make_pair(a, b);
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@ -197,7 +199,9 @@ struct Index {
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Lit OR(Lit a, Lit b)
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{
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return NOT(AND(NOT(a), NOT(b)));
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Lit not_a = NOT(a);
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Lit not_b = NOT(b);
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return NOT(AND(not_a, not_b));
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}
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Lit MUX(Lit a, Lit b, Lit s)
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@ -211,17 +215,24 @@ struct Index {
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return b;
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}
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return OR(AND(a, NOT(s)), AND(b, s));
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Lit not_s = NOT(s);
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Lit a_active = AND(a, not_s);
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Lit b_active = AND(b, s);
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return OR(a_active, b_active);
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}
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Lit XOR(Lit a, Lit b)
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{
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return OR(AND(a, NOT(b)), AND(NOT(a), b));
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Lit not_a = NOT(a);
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Lit not_b = NOT(b);
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Lit a_and_not_b = AND(a, not_b);
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Lit not_a_and_b = AND(not_a, b);
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return OR(a_and_not_b, not_a_and_b);
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}
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Lit XNOR(Lit a, Lit b)
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{
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return NOT(OR(AND(a, NOT(b)), AND(NOT(a), b)));
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return NOT(XOR(a, b));
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}
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Lit CARRY(Lit a, Lit b, Lit c)
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@ -233,7 +244,10 @@ struct Index {
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return AND(a, b);
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}
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}
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return OR(AND(a, b), AND(c, OR(a, b)));
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Lit a_or_b = OR(a, b);
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Lit a_or_b_and_c = AND(c, a_or_b);
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Lit a_and_b = AND(a, b);
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return OR(a_and_b, a_or_b_and_c);
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}
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Lit REDUCE(std::vector<Lit> lits, bool op_xor=false)
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@ -381,7 +395,7 @@ struct Index {
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} else if (cell->type.in(ID($xor), ID($_XOR_))) {
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return XOR(a, b);
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} else if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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return NOT(XOR(a, b));
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return XNOR(a, b);
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} else if (cell->type.in(ID($_ANDNOT_))) {
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return AND(a, NOT(b));
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} else if (cell->type.in(ID($_ORNOT_))) {
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@ -401,7 +415,9 @@ struct Index {
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if (oport == ID::Y) {
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return XOR(ab, c);
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} else /* oport == ID::X */ {
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return OR(AND(a, b), AND(c, ab));
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Lit a_and_b = AND(a, b);
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Lit c_and_ab = AND(c, ab);
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return OR(a_and_b, c_and_ab);
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}
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} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
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Lit c, d;
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@ -412,10 +428,15 @@ struct Index {
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else
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d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
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if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_)))
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return NOT(OR(AND(a, b), AND(c, d)));
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else
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return NOT(AND(OR(a, b), OR(c, d)));
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if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) {
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Lit a_and_b = AND(a, b);
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Lit c_and_d = AND(c, d);
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return NOT(OR(a_and_b, c_and_d));
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} else {
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Lit a_or_b = OR(a, b);
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Lit c_or_d = OR(c, d);
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return NOT(AND(a_or_b, c_or_d));
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}
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} else {
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log_abort();
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}
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@ -436,7 +457,11 @@ struct Index {
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sels.push_back(NOT(s));
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}
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return OR(AND(REDUCE(sels), a), NOT(REDUCE(bar)));
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Lit reduce_sels = REDUCE(sels);
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Lit reduce_sels_and_a = AND(reduce_sels, a);
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Lit reduce_bar = NOT(REDUCE(bar));
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return OR(reduce_sels_and_a, reduce_bar);
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} else if (cell->type == ID($bmux)) {
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SigSpec aport = cell->getPort(ID::A);
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SigSpec sport = cell->getPort(ID::S);
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@ -744,15 +769,15 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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// populate inputs
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std::vector<SigBit> inputs;
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for (auto id : top->ports) {
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Wire *w = top->wire(id);
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log_assert(w);
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++) {
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pi_literal(SigBit(w, i)) = lit_counter;
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inputs.push_back(SigBit(w, i));
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lit_counter += 2;
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ninputs++;
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}
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Wire *w = top->wire(id);
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log_assert(w);
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++) {
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pi_literal(SigBit(w, i)) = lit_counter;
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inputs.push_back(SigBit(w, i));
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lit_counter += 2;
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ninputs++;
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}
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}
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this->f = f;
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@ -760,27 +785,27 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
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write_header();
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// insert padding where output literals will go (once known)
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for (auto id : top->ports) {
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Wire *w = top->wire(id);
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log_assert(w);
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if (w->port_output) {
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for (auto bit : SigSpec(w)) {
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(void) bit;
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", 0);
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f->write(buf, strlen(buf));
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noutputs++;
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Wire *w = top->wire(id);
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log_assert(w);
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if (w->port_output) {
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for (auto bit : SigSpec(w)) {
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(void) bit;
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char buf[16];
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snprintf(buf, sizeof(buf) - 1, "%08d\n", 0);
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f->write(buf, strlen(buf));
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noutputs++;
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}
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}
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}
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}
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auto data_start = f->tellp();
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// now the guts
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std::vector<std::pair<SigBit, int>> outputs;
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for (auto w : top->wires())
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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outputs.push_back({bit, eval_po(bit)});
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}
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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outputs.push_back({bit, eval_po(bit)});
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}
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auto data_end = f->tellp();
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// revisit header and the list of outputs
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@ -885,33 +910,34 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
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Wire *w = top->wire(id);
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log_assert(w);
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if (w->port_input && !w->port_output)
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for (int i = 0; i < w->width; i++)
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pi_literal(SigBit(w, i)) = 0;
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for (int i = 0; i < w->width; i++)
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pi_literal(SigBit(w, i)) = 0;
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}
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HierCursor cursor;
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for (auto box : top_minfo->found_blackboxes) {
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Module *def = design->module(box->type);
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if (!(def && def->has_attribute(ID::abc9_box_id)))
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for (auto &conn : box->connections_)
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if (box->port_dir(conn.first) != RTLIL::PD_INPUT)
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for (auto bit : conn.second)
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pi_literal(bit, &cursor) = 0;
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for (auto &conn : box->connections_)
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if (box->port_dir(conn.first) != RTLIL::PD_INPUT)
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for (auto bit : conn.second)
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pi_literal(bit, &cursor) = 0;
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}
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for (auto w : top->wires())
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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(void) eval_po(bit);
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for (auto w : top->wires()) {
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if (w->port_output) {
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for (auto bit : SigSpec(w))
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(void) eval_po(bit);
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}
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}
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for (auto box : top_minfo->found_blackboxes) {
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Module *def = design->module(box->type);
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if (!(def && def->has_attribute(ID::abc9_box_id)))
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for (auto &conn : box->connections_)
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if (box->port_dir(conn.first) == RTLIL::PD_INPUT)
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for (auto bit : conn.second)
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(void) eval_po(bit);
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for (auto &conn : box->connections_)
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if (box->port_dir(conn.first) == RTLIL::PD_INPUT)
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for (auto bit : conn.second)
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(void) eval_po(bit);
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}
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}
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};
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@ -66,14 +66,7 @@ struct AigMaker
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Cell *cell;
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idict<AigNode> aig_indices;
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int the_true_node;
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int the_false_node;
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AigMaker(Aig *aig, Cell *cell) : aig(aig), cell(cell)
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{
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the_true_node = -1;
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the_false_node = -1;
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}
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AigMaker(Aig *aig, Cell *cell) : aig(aig), cell(cell) {}
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int node2index(const AigNode &node)
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{
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