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17,149 Commits 137 Branches 66 Tags 47 MiB
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17149 Commits

Author SHA1 Message Date
Emil J. Tywoniak 6bb72212d6 Revert "memory: add -bram-register" 
This reverts commit 2bc6ea7f37.
 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak a2e6647339 Revert "memory_bram: add -register" 
This reverts commit b4b5093a14.
 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 12e179bc20 intel_alm: loosen tests 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak ec7375d2cb gowin: loosen tests 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak b995059cef flatten: disable signorm 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak df791a5ac4 ecp5: loosen tests 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak c5ed5163b3 nexus: loosen tests 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 7c083ff204 xilinx_dsp: signorm compatibility 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 5d069fcb3a pmgen: hold sigmap pointer instead of owning it 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak e218c25b30 gowin: rebless LUT counts 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 4e4700b456 equiv_miter: don't copy $input_port 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak a3beac73f6 rtlil_bufnorm: more xlog 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 25d127f0dc design: properly switch signorm mode when restoring saved designs 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak a39ab42b99 equiv_make: don't copy $input_port 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 441a1f47fb rtlil: fix cloneInto in signorm 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 69ff2fb484 rtlil: sigNormalize Module when added to Design in signorm mode 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 81617afa95 rtlil_bufnorm: more xlog 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak a000a7830c intel: register bram celltypes 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 16877b61da rtlil_bufnorm: ignore timing info harder 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 1052e89772 gowin: replace positional arguments in cells_sim.v with named 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak b4bb200dec Revert "techmap: call hierarchy on map files to determine port directions" 
This reverts commit eabbf6d225.
 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 0d62ac186c hierarchy: tolerance for apparent recursive instances in techmap files 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 38255da162 techmap: call hierarchy on map files to determine port directions 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak e78a1a7b3d tests: use memory -bram-register in tests/bram 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 33e5d9340f memory: add -bram-register 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 23523603dc memory_bram: add -register 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak e3c428b6a9 ffmerge: initvals signorm compatibility fixup 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 8e0a0db296 timinginfo: special-case $specify2 in signorm invariant 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak d1c463d685 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak e4d532b886 connect: remove input ports on conflict 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 708bc57e79 opt_dff: sigma harder, FfDataSigMapped 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 274823041b ff: add FfDataSigMapped 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak b58952cf2a opt_dff: temporarily disable signorm due to muxtree traversal 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 451d8471b7 tests: fix rtlil roundtrip test 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak a65d8fbcb9 design: fix signorm commit connectivity to design 2026-05-05 21:35:14 +02:00
Emil J. Tywoniak 992d20071b cxxrtl: ignore $input_port 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 80baffb60e flatten: redo signormalization to work around fanout issue 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak b8f2dfbd5c abstract: fix test signorm 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e75523bf61 signorm: disable passes that use rewrite_sigspecs 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 66af891caa aiger: ignore $input_port 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 99f88aa7e8 check: stitch info about $connect ports together for driver analysis 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e8144f16ac signorm: remove $input cells when leaving 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak d001b407c4 abstract: skip $input_port cells 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e7bffe1d75 flatten: skip $input_port cells in template module 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 6f0ba0060e signorm: skip const when fixing fanout 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak e8dd4868c1 signorm: disable in passes that use swap_names 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 0c9d373458 opt_expr: fix invert_map 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak aa52efb96e satgen: support $connect 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak f481b5e4df rtlil: add dump_sigmap for hacky signorm debugging 2026-05-05 21:35:13 +02:00
Emil J. Tywoniak 1da5f4dfef techmap: disable signorm more 2026-05-05 21:35:13 +02:00