mirror of https://github.com/YosysHQ/yosys.git
satgen: support $connect
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f481b5e4df
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@ -465,6 +465,26 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
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return true;
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}
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if (cell->type.in(ID($connect)))
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{
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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extendSignalWidthUnary(a, b, cell);
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std::vector<int> bb = model_undef ? ez->vec_var(b.size()) : b;
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ez->assume(ez->vec_eq(a, bb));
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if (model_undef)
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{
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std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
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extendSignalWidthUnary(undef_a, undef_b, cell);
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ez->assume(ez->vec_eq(undef_a, undef_b));
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undefGating(b, bb, undef_b);
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}
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return true;
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}
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
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{
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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