 Emil J. Tywoniak
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62cd00aeeb
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rtlil: allow friends to use Wire constructors with a factory token pattern
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2026-07-17 23:47:08 +02:00 |
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Emil J. Tywoniak
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20b0a9934b
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rtlil: allow friends to use Cell constructors with a factory token pattern
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2026-07-17 23:47:08 +02:00 |
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Emil J. Tywoniak
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77dd01edfc
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patcher: start
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2026-07-17 23:47:08 +02:00 |
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Emil J. Tywoniak
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0ff91a58d0
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Revert "tests: use memory -bram-register in tests/bram"
This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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e21e48397e
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tests: use memory -bram-register in tests/bram
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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d19258cd51
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fixup! tests: signorm fix
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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9eafc15df7
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tests: signorm fix
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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abebf4f2db
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signorm: safer indexing if broken invariant
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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628cb4f4ca
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check: check bufnorm too
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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9153c11b56
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check: check signorm indices and wires
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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f2e5bcb86a
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rtlil: publish signorm fanout
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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c9fb05efd6
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opt_merge: newcelltypes
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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6336c0a602
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opt_merge: factor out hashing code across incremental and parallel
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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a582aceaca
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opt_expr: replace invert_map with signorm traversal
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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3010c0fc31
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signorm: add timers
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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fb06c1add5
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rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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061cec3166
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check: fix memory bug in $connect
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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25e7118e4a
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memory_bram: create blackboxes
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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8042d0dc77
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Revert "intel: register bram celltypes"
This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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eaa67e8d36
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Revert "tests: use memory -bram-register in tests/bram"
This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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76d8b2c2ea
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Revert "memory: add -bram-register"
This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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6f09e55c95
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Revert "memory_bram: add -register"
This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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1f745fb781
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intel_alm: loosen tests
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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7cad14da7d
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gowin: loosen tests
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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c8208db681
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flatten: disable signorm
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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cc1bd1d4f1
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ecp5: loosen tests
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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3de496e0c4
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nexus: loosen tests
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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e313678594
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xilinx_dsp: signorm compatibility
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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2291084045
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pmgen: hold sigmap pointer instead of owning it
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2026-07-17 23:38:01 +02:00 |
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Emil J. Tywoniak
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92475ecf62
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equiv_miter: don't copy $input_port
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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83fa720157
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rtlil_bufnorm: more xlog
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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15bd3bcfad
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design: properly switch signorm mode when restoring saved designs
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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52ae92380d
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equiv_make: don't copy $input_port
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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360527af1a
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rtlil: fix cloneInto in signorm
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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2fc93aa711
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rtlil: sigNormalize Module when added to Design in signorm mode
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2026-07-17 23:33:03 +02:00 |
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Emil J. Tywoniak
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f7149450b4
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rtlil_bufnorm: more xlog
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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1b19859e84
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intel: register bram celltypes
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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c40974ee59
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rtlil_bufnorm: ignore timing info harder
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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0c64152d7a
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gowin: replace positional arguments in cells_sim.v with named
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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b0e9dab15a
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Revert "techmap: call hierarchy on map files to determine port directions"
This reverts commit eabbf6d22527f386811c7b507f74f887a258b397.
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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6ca6d4281f
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hierarchy: tolerance for apparent recursive instances in techmap files
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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e82e1aeaad
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techmap: call hierarchy on map files to determine port directions
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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71f01b23f8
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tests: use memory -bram-register in tests/bram
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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eecab792a3
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memory: add -bram-register
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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5b836f1b2b
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memory_bram: add -register
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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8bcec792e2
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ffmerge: initvals signorm compatibility fixup
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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3b1e79d312
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timinginfo: special-case $specify2 in signorm invariant
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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de7f38087d
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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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79386f652f
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connect: remove input ports on conflict
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2026-07-17 23:33:02 +02:00 |
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Emil J. Tywoniak
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f4d180e78f
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opt_dff: sigma harder, FfDataSigMapped
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2026-07-17 23:33:02 +02:00 |
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