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15959 Commits

Author SHA1 Message Date
Emil J. Tywoniak 30ac7d271c satgen: cover $input_port 
(cherry picked from commit d199195785)
 2026-03-10 14:06:45 +01:00
Emil J. Tywoniak c3433bced7 tests: adjust to input_port and init behavior (sketchy) 2026-03-10 14:05:37 +01:00
Emil J. Tywoniak 45a254cf61 tests: adjust to input_port and init behavior (sketchy) 2026-03-10 14:02:46 +01:00
Emil J. Tywoniak 8375f11fa5 wreduce: fixup initvals after setPort 2026-03-10 14:01:57 +01:00
Emil J. Tywoniak 298b755fb7 modtools: fix database sanity on wire name swap 
(cherry picked from commit c75d80905a)
 2026-03-09 23:46:53 +01:00
Emil J. Tywoniak 58ba984498 ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire 2026-03-09 23:38:10 +01:00
Emil J. Tywoniak 25edde1c3c tests: adjust to input_port and init behavior (sketchy) 2026-03-09 21:21:45 +01:00
Emil J. Tywoniak d2bc970ef9 rtlil: fix zero width SigSpec crash in signorm setPort unsetPort 2026-03-09 21:20:23 +01:00
Emil J. Tywoniak bdce610f3d bug2920: disable 2026-03-09 16:37:30 +01:00
Emil J. Tywoniak b206223c40 rtlil_bufnorm: fix cell deletion deferral bug 2026-03-07 01:10:04 +01:00
Emil J. Tywoniak b7c97ba743 tests: adjust to input_port and init behavior (sketchy) 2026-03-07 01:08:57 +01:00
Emil J. Tywoniak 7c5128a08a check: don't fail on $input_port 2026-03-07 00:42:01 +01:00
Emil J. Tywoniak c6b9f5d8ff mem: fix signorm cell type morph 2026-03-07 00:41:24 +01:00
Jannis Harder eae87b3161 WIP half broken snapshot 2025-10-06 14:39:25 +02:00
Jannis Harder ea0ee069fb WIP remove dead code 2025-10-04 14:40:08 +02:00
Emil J 7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops 
Reduce hashops verbiage in `OptMergePass`
 2025-09-30 19:34:44 +02:00
Emil J 60c551f961
Merge pull request #5400 from YosysHQ/emil/github-contribution-template-update 
Update contribution templates
 2025-09-30 11:03:49 +02:00
Emil J. Tywoniak dc7764e247 .github: typos 2025-09-30 11:03:19 +02:00
Miodrag Milanović 330a5fc101
Merge pull request #5402 from YosysHQ/micko/extensions 
Force linking log_compat when extensions are linked
 2025-09-30 09:10:04 +02:00
Miodrag Milanovic e6fa0223c8 Force linking log_compat when extensions are linked 2025-09-30 08:44:31 +02:00
github-actions[bot] 5fd2aecd90 Bump version 2025-09-30 00:23:05 +00:00
Emil J. Tywoniak b86cc0d9b3 docs: replace Slack with Discourse in extensions writing guide 2025-09-29 23:20:06 +02:00
Emil J. Tywoniak b2adaeec69 .github: replace Slack and GitHub Discussions with Discourse in issue templates 2025-09-29 23:03:54 +02:00
Emil J. Tywoniak 4c17ac5ac2 .github: suggest Discourse in PR template 2025-09-29 23:03:29 +02:00
ShinyKate 30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff 
read_blif: Represent sequential elements with gate cells
 2025-09-29 08:21:16 -05:00
Jannis Harder 47639f8a98
Merge pull request #5388 from jix/bufnorm-followup 
Refactor and fixes to incremental bufNormalize + related changes
 2025-09-29 15:15:29 +02:00
Jannis Harder 6a7372626a
Merge pull request #5389 from jix/sva_continue 
verific: New `-sva-continue-on-error` import option
 2025-09-29 15:07:54 +02:00
Emil J 87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic 
Move `OptMerge` cell filtering logic to happen while building the cell vector
 2025-09-29 15:03:01 +02:00
Martin Povišer 04c7013f0e
Merge pull request #5399 from povik/opt_hier-bug 
opt_hier: Fix two optimizations conflicting
 2025-09-29 14:53:54 +02:00
Akash Levy acf3a6606f Small gitignore fixes 2025-09-29 12:11:59 +01:00
Martin Povišer a9318db2fa opt_hier: Adjust messages 2025-09-29 12:27:27 +02:00
Martin Povišer ffe2f7a16d opt_hier: Fix two optimizations conflicting 
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
 2025-09-29 12:27:27 +02:00
Miodrag Milanović 69770a844e
Merge pull request #5396 from akashlevy/pyosys_fix 
BUGFIX: pyosys cannot parse header with omitted function args
 2025-09-29 10:20:31 +02:00
Jannis Harder 86fb2f16f7 bufnorm: Refactor and fix incremental bufNormalize 
This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
 2025-09-29 08:21:28 +02:00
Jannis Harder cbc1055517 opt_clean: Fix debug output when cleaning up bufnorm cells 2025-09-29 08:21:28 +02:00
Jannis Harder 90669ab4eb aiger2: Only fail for reachable undirected bufnorm helper cells 
The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.

Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.

With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
 2025-09-29 08:21:28 +02:00
Jannis Harder 9396e5e5fe portarcs: Ignore all bufnorm helper cells 
The `portarcs` pass was already ignoring `$buf` cells when loading
timing data, but now bufnorm will also emit `$input_port` and `$connect`
helper cells, which need to be ignored as well.
 2025-09-29 08:21:28 +02:00
Akash Levy 4b6b254e31 pyosys cannot parse header with omitted function args 2025-09-28 01:37:30 -07:00
Jannis Harder 4bb4b6c662 verific: Extend -sva-continue-on-err to handle FSM explosion 
This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
 2025-09-27 21:13:02 +02:00
Jannis Harder ce5d04a42f hierarchy: Suggest more specific command to skip unsupported SVA 2025-09-26 18:41:26 +02:00
KrystalDelusion 7ebd972165
Merge pull request #5277 from YosysHQ/krys/fix_4983_alt 
autoname: Avoid integer overflow
 2025-09-26 14:11:20 +12:00
github-actions[bot] 6a5d956747 Bump version 2025-09-26 00:22:24 +00:00
Krystine Sherwin 941ba3b745
autoname.ys: Extra check for rename order 
Disabling comparison with best score will cause this check to fail.  Preferred names will not be possible if $name2 has not yet been renamed.
 2025-09-26 11:36:23 +12:00
Krystine Sherwin fef6bdae6c
autoname.cc: Return number of renames 
Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
 2025-09-26 11:05:50 +12:00
Emil J 8c8d18f2d8
Merge pull request #5392 from rocallahan/opt-merge-cleanup 
Some small readability improvements to `OptMergeWorker`
 2025-09-25 12:15:33 +02:00
Martin Povišer 29e0144ebc
Merge pull request #5381 from povik/abc9-multilib 
Support multiple lib files in abc9_exe
 2025-09-25 09:45:09 +02:00
Robert O'Callahan 4d209c187d Switch OptMergeWorker cell type switching to use IdString::in() 2025-09-25 03:06:58 +00:00
Robert O'Callahan 1c73011e7e Swap SigSpecs using std::swap with moves 2025-09-25 03:04:17 +00:00
github-actions[bot] 3f29cd7f4e Bump version 2025-09-25 00:22:44 +00:00
Jannis Harder 83dd99efb7 verific: New `-sva-continue-on-error` import option 
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
 2025-09-24 18:58:54 +02:00