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18230 Commits

Author SHA1 Message Date
Akash Levy 400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy 8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Roland Coeurjoly 5ea2c6e6e5 Assume x values for missing signal data in FST 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-02 12:08:48 +02:00
Martin Povišer ec42b42bd9 cellmatch: Size the `lut` attribute 2024-10-02 11:29:54 +02:00
Akash Levy ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy afe3b18a04 Another try on mem fix 2024-10-01 21:57:59 -07:00
Akash Levy 73902607cd Smallfix test 2024-10-01 07:46:56 -07:00
Akash Levy af10f5e4f6 Update 2024-10-01 04:40:49 -07:00
Emil J. Tywoniak 997cb30f1f cxxrtl: test stream operator 2024-10-01 13:25:07 +02:00
Akash Levy a0ebd9545a Try again 2024-10-01 04:13:01 -07:00
Akash Levy 3b8bc8098f Smallfix 2024-10-01 04:03:45 -07:00
Akash Levy 16b1eb1699 Update fix 2024-10-01 03:42:32 -07:00
Roland Coeurjoly 76c615b2ae Fix: handle VCD variable references with and without whitespace 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-10-01 11:51:20 +02:00
Akash Levy dd9687fc4c Add way to disable memory init 2024-10-01 01:32:29 -07:00
Akash Levy 776661ab40 Update dep 2024-09-30 18:59:44 -07:00
Akash Levy 7442bfaa2f
Merge branch 'YosysHQ:main' into main 2024-09-30 18:58:14 -07:00
github-actions[bot] 1bf908dea8 Bump version 2024-10-01 00:23:05 +00:00
Miodrag Milanović 500db6acc6
Merge pull request #4621 from RCoeurjoly/roland/get_vcd2fst 
Add "Get vcd2fst" step to test-yosys job
 2024-09-30 21:38:39 +02:00
Mohamed Gaber 35c8ad61ac
cli/python: error-checking, python interpreter bugfix 
* Less brittle method of adding script dirname to sys.path
* Check if scriptfp successfully opens before using it
* Move `log_error` to after `PyErr_Print()` is called
 2024-09-30 17:38:43 +03:00
Roland Coeurjoly 5fca9b867d Add Get vcd2fst step to test-yosys job 
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-30 16:25:32 +02:00
Akash Levy e21d007791 Bump dep version 2024-09-30 02:54:46 -07:00
Akash Levy ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
github-actions[bot] 59404f8ce5 Bump version 2024-09-30 00:21:26 +00:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Mike A. 95a2099c90
Allow whitespace in `tee` command paths 2024-09-29 17:15:59 +02:00
Akash Levy 599cebfca5 Include pmuxtree 2024-09-29 05:31:51 -07:00
Akash Levy 49d948d873 Fix splitfanout: keep original cell, add new cells to driver db to fix net messup 2024-09-29 03:07:07 -07:00
Akash Levy 9ecb4e798e Update deps 2024-09-28 19:49:07 -07:00
Akash Levy 0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy 5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy 9f4d385e35 Update yosys-slang 2024-09-27 03:06:10 -07:00
Akash Levy 7f05f0b273 Fix muxadd peepopt to track bitsplit 2024-09-27 02:28:32 -07:00
Akash Levy b1383a80cf Make renaming nicer for bmuxmap -pmux 2024-09-27 00:54:05 -07:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie 023f029dcf opt_reduce: keep at least one input to $reduce_or/and cells 2024-09-25 16:21:19 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
Akash Levy dbaaf78044 Iterate to new wire 2024-09-24 16:47:35 -07:00
Akash Levy ebf8783b4b Fixup parameters 2024-09-24 13:55:09 -07:00
Martin Povišer 3e3515e7d9 log: Never silence `log_cmd_error` 
Add extra handling to arrange for `log_cmd_error` never being silenced
by the command line `-v N` option. Similar path for `log_error` exists
already.
 2024-09-24 17:47:46 +02:00
George Rennie 58af70624f opt_demorgan: skip zero width cells 2024-09-24 14:24:59 +01:00
George Rennie b788de9329 smtbmc: escape path identifiers 
* also changes the print format for cover statements to be more uniform
  with the asserts, allowing easier parsing of cover path
* this allows diambiguation of properties with the same name but
  different paths (see https://github.com/YosysHQ/sby/issues/296)
 2024-09-24 03:01:49 +01:00
Akash Levy 08fe6f66aa Fix functional 2024-09-23 06:56:12 -07:00
Akash Levy a5c115f333 Update yosys-slang dep 2024-09-23 06:28:46 -07:00
Akash Levy 9193b0e324
Merge branch 'YosysHQ:main' into main 2024-09-23 06:27:58 -07:00
N. Engelhardt 8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail 2024-09-23 15:19:48 +02:00
Akash Levy ed2c65314b Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
Akash Levy 9e9d4359d4 Smallfix 2024-09-23 05:57:09 -07:00
Akash Levy 6b9c45a841 Enable only the test suites we need 2024-09-23 05:39:56 -07:00