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18230 Commits

Author SHA1 Message Date
Martin Povišer de8a2fb936 aiger2: Fix duplicate symbols on multibit ports 2024-09-17 13:55:58 +02:00
Martin Povišer 5671c10173 aiger2: Add strashing option 2024-09-17 13:55:58 +02:00
Martin Povišer fa39227416 aiger2: Support `$pos` 2024-09-17 13:55:58 +02:00
Martin Povišer fb26945a20 Start an 'aiger2' backend 2024-09-17 13:55:58 +02:00
Martin Povišer 4cfdb7ab50 Adjust operation naming in aigmap test 2024-09-17 13:55:58 +02:00
Martin Povišer a553b7c0c7
Merge pull request #3967 from YosysHQ/claire/bufnorm 
Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command
 2024-09-17 11:27:23 +02:00
Martin Povišer eeffca9470 simlib: Add `$buf` disclaimer 2024-09-17 10:46:20 +02:00
Martin Povišer e13ace675e dump: Update help after option removal 2024-09-17 10:46:20 +02:00
Martin Povišer 38de01807e Mark `bufnorm` experimental 2024-09-17 10:46:20 +02:00
Martin Povišer 865df26fac Adjust buf-normalized mode 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 4d469f461b Add coarse-grain $buf buffer cell type 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf 32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Akash Levy e4f1f5a96c
Merge branch 'YosysHQ:main' into main 2024-09-16 19:14:49 -07:00
Akash Levy 44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
github-actions[bot] c8846243c2 Bump version 2024-09-17 00:16:41 +00:00
Akash Levy 76b072151d Bump yosys-slang 2024-09-16 07:12:31 -07:00
Akash Levy e4edea1b25 Update 2024-09-16 07:03:38 -07:00
Akash Levy 210ec6585f
Merge branch 'YosysHQ:main' into main 2024-09-16 06:59:25 -07:00
Emil J f8ad371254
Merge pull request #4594 from yrabbit/cpu-wip 
Gowin. Add the EMCU primitive.
 2024-09-16 15:41:14 +02:00
Emil J 52382c6544
Merge pull request #4583 from YosysHQ/emil/clock_gate 
clockgate: centralize clock enables out of FFs
 2024-09-16 15:41:01 +02:00
Emil J. Tywoniak f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
Akash Levy 1eb887238e Bump yosys-slang dep 2024-09-12 12:23:59 -07:00
Akash Levy 285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
github-actions[bot] 229d1ea937 Bump version 2024-09-12 00:19:38 +00:00
Akash Levy 985de62d3c
Merge branch 'YosysHQ:main' into main 2024-09-11 16:01:37 -07:00
Mohamed Gaber 8dac27108e
Typos 2024-09-11 21:45:51 +03:00
Mohamed Gaber 738b5eef0b
Add dirname of script file to sys.path 
This matches the behavior of running a Python interpreter, where the
first element of sys.path is the dirname of the script being run.

This allows importing of files and modules in the same directory without
messing with PYTHONPATH or similar.
 2024-09-11 21:45:51 +03:00
Mohamed Gaber 38f9e6c3a2
-y flag for libyosys Python scripts 
This adds a Python equivalent to the `-c` option, where scripts importing `libyosys` can be imported and used.

Most of the work for this was already done to enable Python passes a couple years back, so this is a relatively small changeset.
 2024-09-11 21:45:51 +03:00
Emil J. Tywoniak 1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Akash Levy a96337110f Bump version 2024-09-11 04:16:34 -07:00
Martin Povišer 34572708d5
Merge pull request #4595 from YosysHQ/emil/internal_stats-astnode 
internal_stats: astnode (sizeof)
 2024-09-11 12:21:29 +02:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Emil J. Tywoniak 8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
YRabbit ab35dff702 Gowin. Add the EMCU primitive. 
EMCU is a micro-processor based on ARM Cortex-M3 embedded in the
GW1NSR-4C chip used in the Tangnano4k board.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-09-11 10:18:51 +10:00
Akash Levy 47a261f9c4 Bump third party 2024-09-10 13:34:28 -07:00
Akash Levy 02931ebfd2
Merge branch 'YosysHQ:main' into main 2024-09-10 11:23:27 -07:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
github-actions[bot] 6937241012 Bump version 2024-09-10 00:19:34 +00:00
Akash Levy 7ff3bff014 Add tee 2024-09-09 12:34:43 -07:00
Emil J. Tywoniak 7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak dc039d8be4 clockgate: test fine-grained cells 2024-09-09 21:03:22 +02:00
Akash Levy d427b78afd
Merge branch 'YosysHQ:main' into main 2024-09-09 10:16:51 -07:00