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4894 Commits

Author SHA1 Message Date
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella 66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak 4ab22cbb97 abc: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Miodrag Milanović 05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix 
abc9: preserve topological-loop asserts with targeted SCC fallback
 2026-03-04 11:09:38 +01:00
Miodrag Milanovic b7d013e6bf Fix help message for equiv passes 2026-03-04 07:46:40 +01:00
Emil J. Tywoniak 6f74c54c02 async2sync: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak a53104379d clk2fflogic: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
Andrew Pullin 5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Miodrag Milanović 0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify 
abc9: verify post-mapping equivalence by default
 2026-02-20 13:41:11 +01:00
Krystine Sherwin 094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
nella 01e89a8f9e Remove cell mentions. 2026-02-18 09:29:35 +01:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
Emil J. Tywoniak 77f64de997 satgen: move report_missing_model here from equiv.h 2026-02-16 17:01:09 +01:00
Emil J. Tywoniak 81ea922512 sat: use the same cell import warnings as equiv 2026-02-16 16:54:26 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Emil J fba29ea8f1
Merge pull request #5679 from YosysHQ/emil/abc9-remove-liberty 
abc9: remove -liberty
 2026-02-11 12:36:29 +01:00
Emil J. Tywoniak 915912cc76 abc9: remove -dont_use 2026-02-11 11:39:09 +01:00
Emil J. Tywoniak c4094e457b abc9: remove -genlib, -constr 2026-02-11 11:34:54 +01:00
Emil J. Tywoniak 5a46106a46 abc9: remove -liberty 2026-02-11 01:04:50 +01:00
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00
Gus Smith f062a0c8d6 Typo 2026-02-06 17:26:08 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Robert O'Callahan 7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE 
(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
 2026-02-04 17:19:10 +13:00
Emil J. Tywoniak ed53ff2f49 equiv_simple, equiv_induct: fix config 2026-02-03 18:37:39 +01:00
Emil J. Tywoniak 8d1c1faf82 equiv_simple, equiv_induct: error by default on missing model, add -ignore-unknown-cells 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 8e73e2a306 sat: add -ignore-unknown-cells instead of -ignore_unknown_cells for consistency 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 000be270ca equiv_simple, equiv_induct: refactor 2026-02-03 17:54:46 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Robert O'Callahan 9c56c93632 Add missing newlines to some 'log_error's 2026-01-30 01:52:19 +00:00
Robert O'Callahan 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal 2026-01-30 01:52:19 +00:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Robert O'Callahan 139c38ecfa Dump module details when design_equal fails 2026-01-28 18:32:12 +00:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 6a6e5f0f54 linux_perf: only include unistd on Linux 2026-01-28 03:44:33 -08:00
Natalia fc2b7c317f linux_perf: include unistd for POSIX I/O 2026-01-28 03:14:20 -08:00
Emil J 75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help 
linux_perf: mark internal, fix help formatting
 2026-01-28 11:06:08 +01:00
Krystine Sherwin 8ed7ac04d8
linux_perf.cc: Fix overlength codeblock 2026-01-28 08:17:56 +13:00
Krystine Sherwin 4031310ebb
linux_perf.cc: Use formatted_help 
Gets the codeblock formatting better.

Also fold the on|off into a single usage.
 2026-01-28 08:10:31 +13:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J. Tywoniak ef3b2b0380 linux_perf: mark internal, fix help formatting 2026-01-26 22:59:20 +01:00
nella 9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella 5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
Emil J 29a9e42b64
Merge pull request #5628 from rocallahan/linux-perf-ctl 
Add `linux_perf` command to turn Linux perf recording on and off.
 2026-01-26 19:32:55 +01:00
nella 8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
Emil J 673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Robert O'Callahan 7d53d64a47 Make the call to `compare_signals()` easier to read. 
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
 2026-01-24 02:01:05 +00:00
Robert O'Callahan 2468b391bf Make `compare_signals` produce a total order. 
Currently when `s1` and `s2` are different bits of the same wire,
it is possible for both `compare_signals(s1, s2)` and `compare_signals(s2, s1)` to
return false. This means the calling code will call `assign_map.add()` for
both `s1` and `s2`, which doesn't make much sense --- one of `s1` or `s2`
should be consistently preferred.

So fix that by preferring the `SigBit` with the smaller bit offset.
 2026-01-24 02:00:33 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
nella 0e4282d442 Add more opt_dff documentation. 2026-01-23 09:17:14 +01:00
Robert O'Callahan 4f53612725 Add `linux_perf` command to turn Linux perf recording on and off. 
This is extremely useful for profiling specific passes.
 2026-01-23 01:44:57 +00:00
Robert O'Callahan e87bb65956 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-01-23 01:14:35 +00:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
nella f6eba53d1f Fix copyright header. 2026-01-21 14:52:19 +01:00
nella 2c12545cf3 opt_dff restructure. 2026-01-21 10:08:44 +01:00
Lofty 5a9d73369a abc9: verify post-mapping equivalence by default 2026-01-20 09:58:35 +00:00
Martin Povišer 90673cb0a2 techmap: Use `-icells` mode of frontend instead of type fixup 2026-01-19 16:49:49 -08:00
Emil J. Tywoniak c3f36afe7f opt_balance_tree: mark experimental 2026-01-19 12:01:25 +01:00
Robert O'Callahan 28c199fbbd Fix warning about unused variable in `dffunmap`. 2026-01-19 03:25:09 +00:00
KrystalDelusion 8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err 
Improve error handling in sim
 2026-01-19 09:51:12 +13:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width 
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
 2026-01-14 14:58:53 -08:00
Natalia 60ac3670cb Fix truncation issue in opt_balance_tree pass 
Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.

For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)

Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
 2026-01-14 13:14:56 -08:00
Natalia Kokoromyti 6aef8ea8ab Add missing <deque> include for MSVC compatibility 2026-01-13 15:31:46 -08:00
nataliakokoromyti 8a596f330a Update lut2mux.cc 2026-01-13 15:02:17 -08:00
nataliakokoromyti 40f9e235de
Update lut2mux.cc 2026-01-13 14:45:46 -08:00
nataliakokoromyti 6a93a94d9f
fix line 2026-01-13 14:44:51 -08:00
nataliakokoromyti c305c426eb
restore extra_args 2026-01-13 14:43:52 -08:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Miodrag Milanović 51b210c93c
Merge pull request #5600 from YosysHQ/fix_musllinux 
musllinux fix so wheels build can work
 2026-01-13 07:08:04 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Miodrag Milanovic b3b71df07c musllinux fix so wheels build can work 2026-01-12 15:38:45 +01:00
Miodrag Milanović 72690062a1
Merge pull request #5599 from YosysHQ/musllinux_fix 
musllinux fix so wheels build can work
 2026-01-12 14:00:00 +01:00
Emil J f193dd0a28
Merge pull request #5594 from rocallahan/sdc-workaround 
Check for missing port in SDC code to work around compiler bug
 2026-01-12 11:22:25 +01:00
Miodrag Milanovic 2b12b74121 musllinux fix so wheels build can work 2026-01-11 15:23:38 +01:00
Robert O'Callahan 37347aacb2 Check for missing port in SDC code 
I am getting weird crashes on `main` in `tests/sdc/alu_sub.ys` which I traced to a null `Wire*`
in `SdcObjects::constrained_ports`. The null `Wire*` is being set in the `SdcObjects`
constructor. I don't understand what's going on here, so I added this check to detect the
missing wire early ... and that made the crash go away. Compiler bug maybe? I have
`Debian clang version 19.1.7 (3+build5)`, default build configuration.

Anyway this code seems fine to have.
 2026-01-10 04:00:17 +00:00
KrystalDelusion cc3d569ade
Merge pull request #5591 from YosysHQ/krys/clean_empty_switch 
Improve handling of empty switches
 2026-01-09 11:52:27 +13:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00