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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00
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17,740 Commits 155 Branches 70 Tags
itsaflower-patch-1
Commit Graph
7 Commits
Author SHA1 Message Date
nellaandIztok Jeras 9050446798 Add latch tests, extend dff tests.
Co-authored-by: Iztok Jeras <[email protected]>
2026-08-10 10:59:03 +02:00
Emil J. Tywoniak c50290fdab dfflibmap: fix formal verilog test so that it actually maps all flops 2026-07-27 22:08:39 +02:00
Emil J. Tywoniak 1a1d9494da dfflibmap: check formal verilog test actually maps all flops 2026-07-27 22:06:22 +02:00
Emil J. Tywoniak 12b443e71c dfflibmap: consistent clk2fflogic usage in test 2026-03-19 19:48:25 +01:00
Emil J. Tywoniak 5b4603c54f dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate 2026-03-03 10:35:03 +01:00
Emil J. Tywoniak 024408004a dfflibmap: allow formal dffsr mapping tests with clk2fflogic 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak 2dddc53ccf dfflibmap: test dffsr and dffsre from proc with equiv 2026-03-03 10:34:29 +01:00
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