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2600 Commits

Author SHA1 Message Date
Miodrag Milanovic 474d0d7b2e cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8953007483 Use generic testing on few more places 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f96fa5ff00 cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8ff28a2a86 add prep 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 336a06d091 Add common.mk 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c04d724337 report on summary 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 45bb0413bf Look for all result files 2026-04-16 11:00:44 +02:00
Miodrag Milanovic b361569abf Save results, and create summary and report 2026-04-16 11:00:44 +02:00
Miodrag Milanovic ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic a2e1fbcfc6 Enabled realmath that was disabled for some reason 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2f9e35acb8 Fix deprecation warning 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 712ce93501 Clean some seed-tests outputs 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 999255e40c Clean some seed-tests outputs 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 2774671346 Cleanup for abcopt-tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic fc55f16fae Ignore some generated files 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 3c2adfb523 Do not write to console for makefile-tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 8f7e5e9449 Make sure targets are built for tests 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 5494000fd7 Move clean for tests in proper Makefile 2026-04-16 11:00:44 +02:00
Miodrag Milanovic c99855535a Split vanilla-test to separate Makefile 2026-04-16 11:00:44 +02:00
Emil J. Tywoniak 3e45f9729e fix $specrule port naming 2026-04-13 22:34:46 +02:00
nella fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella c3c577f333 Fix test cases. 2026-04-13 12:48:05 +02:00
nella 42c309347b Clarify. 2026-04-13 12:48:05 +02:00
nella 4f4c820f73 Cleaned up CSA tests. 2026-04-13 12:48:05 +02:00
nella 9cc2e7d95e rm misc comments. 2026-04-13 12:48:05 +02:00
nella 9dc408eea7 CSA add alumacc related tests. 2026-04-13 12:48:05 +02:00
nella fc9adae9a2 Consolidate csa tests. 2026-04-13 12:48:05 +02:00
nella ab1c423692 Tighten csa tests. 2026-04-13 12:48:05 +02:00
nella cfee6bb4af Add more robsutness tests. 2026-04-13 12:48:05 +02:00
nella 6b0caedcdd Add chain tests and tighten synthesis assertions for csa. 2026-04-13 12:48:05 +02:00
nella 7183016910 Edge case tests. 2026-04-13 12:48:05 +02:00
nella 1a4a41812c Add csa synth tests. 2026-04-13 12:48:05 +02:00
nella 4c4c5cf15a Add structural tests for csa_tree. 2026-04-13 12:48:05 +02:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
Gus Smith 6a5fea1b27 Regression test for #5765 2026-03-30 08:59:28 -07:00
Miodrag Milanovic 417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanović cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Emil J 7b2ab9b245
Merge pull request #5763 from YosysHQ/emil/c-slow-init 
genrtlil: fast memory initialization
 2026-03-23 10:21:21 +00:00
Emil J. Tywoniak 12b443e71c dfflibmap: consistent clk2fflogic usage in test 2026-03-19 19:48:25 +01:00
Emil J 9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 
setundef: respect selection for cells, processes, and connections
 2026-03-18 22:53:06 +00:00
Emil J. Tywoniak 27737c6e2e rtlil: add remove2 unit test 2026-03-18 23:33:35 +01:00
Lofty c4cc53a72e synth: fix after abc -fast removal 2026-03-18 17:59:58 +01:00
Emil J c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean 
Parallelize `opt_clean` pass
 2026-03-16 09:52:34 +00:00
abhinavputhran 314d01b35f changed rtlil to verilog. setundef_selection_ff stays rtlil because we use specific cell names if write in verilog yosys assign name that can change 2026-03-08 20:14:03 -04:00
abhinavputhran 47c2257f82 setundef: more tests! and wire selection in -init mode 2026-03-08 19:41:31 -04:00
abhinavputhran c23ba3f917 I think CI runs within the tests directory based on error so I changed the file path 2026-03-08 18:15:35 -04:00
abhinavputhran 5048dac854 setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
Lofty 050483a6b2
Merge pull request #5698 from YosysHQ/lofty/analogdevices 
synth_analogdevices: synthesis for Analog Devices EFLX FPGAs [sc-273]
 2026-03-06 08:57:59 +00:00
Miodrag Milanovic 602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Robert O'Callahan 1260fda83a Add 'init' attributes to RTLIL fuzzing 2026-03-06 02:20:08 +00:00
Robert O'Callahan cdfc586f18 Add unit tests for `ConcurrentWorkQueue` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 1e96328ede Add some tests for `ShardedHashSet` 2026-03-06 02:20:08 +00:00
Robert O'Callahan 3910d569da Add unit tests for `ConcurrentQueue` and `ThreadPool` 2026-03-06 02:20:08 +00:00
Robert O'Callahan ac55935a68 Add unit-tests for `ParallelDispatchThread` and friends 2026-03-06 02:20:08 +00:00
Robert O'Callahan 7f3b11e56b Add test that connects a wire with `init` to a constant 2026-03-06 02:20:08 +00:00
Justin Zaun 9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
 2026-03-05 16:04:23 +01:00
Emil J 629bf3dffd
Merge pull request #5630 from apullin/array-assignment 
ast: Add support for array-to-array assignment
 2026-03-05 11:10:12 +00:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Lofty 39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Lofty 6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Andrew Pullin 6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00
nella 66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak 6d4736269b newcelltypes: extend testing 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak ae10e9e955 pyosys: disable test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak f594014bef newcelltypes: proper bounds for unit test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak d91e1c8607 newcelltypes: test against builtin_ff_cell_types 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 2d7d6ca10b newcelltypes: unit test 2026-03-04 12:22:14 +01:00
Miodrag Milanović 05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix 
abc9: preserve topological-loop asserts with targeted SCC fallback
 2026-03-04 11:09:38 +01:00
Emil J. Tywoniak 5b4603c54f dfflibmap: fix formal $dffsr tests with sat, prove "no s&r" assumption only needed when appropriate 2026-03-03 10:35:03 +01:00
Emil J. Tywoniak 024408004a dfflibmap: allow formal dffsr mapping tests with clk2fflogic 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak 2dddc53ccf dfflibmap: test dffsr and dffsre from proc with equiv 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak c13a623dbc dfflibmap: test dffsr with either priority liberty file 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak ffb76a3486 dfflibmap: test dffsr mapping without assume 2026-03-03 10:34:29 +01:00
likeamahoney e9442194f2 support automatic lifetime qualifier on procedural variables 2026-02-27 20:42:52 +03:00
Andrew Pullin 5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Gus Smith c0f1654028 Expand test into three tests for three cases 
(1) no check, (2) check with warning, (3) check
with error. Previously the single test was not
testing all cases, as it was exiting after the
first error.
 2026-02-23 10:27:36 -08:00
Krystine Sherwin fd311c5501 tests/arch/gowin: Add wr_en test 2026-02-22 09:00:37 +01:00
Gus Smith b454582f54 Detect undriven and error/warn 2026-02-20 11:00:59 -08:00
Emil J 74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Emil J 53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion 
modtools: fix database sanity
 2026-02-20 10:49:28 +01:00
Emil J. Tywoniak abc7563a35 modtools: add ModIndex unit test 2026-02-18 22:15:44 +01:00
Miodrag Milanović ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Chris Hathhorn 1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
Miodrag Milanović e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith e3db8fee6f
Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub 
Add support for subtract in preadder
 2026-02-11 08:02:18 -08:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Gus Smith b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Gus Smith 3f01d7a33a Add test 2026-02-03 14:41:08 -08:00
Emil J. Tywoniak 91b226b4d4 specify: fix test 2026-02-03 18:40:32 +01:00
Emil J. Tywoniak c768e55983 ice40: fix dsp_const test 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 2efd0247a1 opt_hier: fix test 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Natalia 61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia 7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia 8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia 74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J 5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
nella a3c9716f18 OptDff fix unit tests. 2026-01-26 22:35:25 +01:00
Emil J 673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan 32e96605d4 Don't update `used_signals` for retained wires in `rmunused_module_signals`. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Emil J f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
KrystalDelusion 125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J 317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J 5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Gus Smith 9ed56ac72c Mimic pattern of how other tests build plugins 
Seems like using --build isn't supported in CI
 2026-01-20 10:44:47 -08:00
Gus Smith bd9dbea4ea Add -I 2026-01-20 10:07:44 -08:00
Gus Smith 0f6ef77775 Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
Gus Smith 491276983e Add test 2026-01-19 18:34:55 -08:00
Krystine Sherwin 0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Natalia cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Natalia ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
Emil J. Tywoniak ddf3c6c8b7 blif: add -gatesi test 2026-01-14 21:41:56 +01:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Natalia Kokoromyti 8b6925c5b0 Add opt_balance_tree pass for timing optimization 
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
 2026-01-13 14:20:11 -08:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
nella b332279baf
Merge pull request #5592 from YosysHQ/gus/5503-yw-load-error-msg 
More helpful error messages when loading Yosys Witness files with `yosys-smtbmc`
 2026-01-13 12:00:06 +01:00
Emil J cc25ccfcd7
Merge pull request #5559 from nataliakokoromyti/upstream-lut2bmux 
add lut2bmux
 2026-01-12 16:09:13 +01:00
Robert O'Callahan 41a098172d Expect an error from the bug5574.ys test 2026-01-08 09:58:01 +01:00
Roland Coeurjoly f1fc704c84 abc: handle ABC script errors instead of hanging 2026-01-07 23:46:33 +01:00
Krystine Sherwin 9a09758f56
Test empty switches 2026-01-07 13:21:33 +13:00
Gus Smith 9f77465170 Add test 2026-01-06 16:19:04 -08:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Emil J 2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers 
opt_expr: avoid multiple drivers in test
 2026-01-06 14:54:55 +01:00
Natalia 11b0e7ad92 add lut2bmux 2026-01-06 14:48:16 +01:00
Miodrag Milanović d523c88c3c
Merge pull request #5573 from rocallahan/increase-timeout 
Increase test timeout to 10 seconds
 2025-12-29 12:38:34 +01:00
Robert O'Callahan 99d7ab9c42 Increase test timeout to 10 seconds 
On my machine, this test regularly times out when doing "make -j" (which defaults to 128).
The high degree of parallelism seems to slow down the spwaning of ABC processes.
 2025-12-29 04:35:05 +00:00
Natalia 721b504479 lut2mux: add -word option and test 2025-12-23 05:57:40 -08:00
Robert O'Callahan 9ee51c8f27 Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it. 2025-12-22 21:56:26 +00:00
Robert O'Callahan 914e14946d Implement design_equal command 2025-12-21 21:47:40 +00:00
Emil J. Tywoniak 856d455065 opt_expr: avoid multiple drivers issue #4792 in combined assign tests 2025-12-19 18:32:56 +01:00
Emil J. Tywoniak 772d821fb0 opt_expr: reindent test 2025-12-19 18:32:56 +01:00
N. Engelhardt 45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Miodrag Milanović d861a26e49
Merge pull request #5504 from nataliakokoromyti/verific-run-test-bugfix 
Fix Verific run-test.sh
 2025-12-17 11:08:44 +01:00
nataliakokoromyti 2ded4bd893
Update run-test.sh 
fix: preserve newline at eof
 2025-12-16 04:16:03 -08:00
Krystine Sherwin c69be9d767
Missed an iverilog 
Should now still report an iverilog issue if `iverilog` doesn't exist.
 2025-12-15 10:31:17 +13:00
Krystine Sherwin 24f4902156
Don't mention iverilog if the error wasn't from iverilog 2025-12-15 10:17:19 +13:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Krystine Sherwin 4da0c552dd
tests/aiger: Fix pipe hiding diff exit status 2025-12-12 11:26:24 +13:00
Yannick Lamarre 54b278d574 Add tests for implicit wires in generate blocks. 
Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
 2025-12-10 14:43:42 +01:00
Emil J e08e9119ee
Merge pull request #5516 from rocallahan/limit-threads 
Limit thread usage in tests
 2025-12-10 13:45:07 +01:00
Emil J 46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input 
aiger2: fix empty cell input
 2025-12-04 16:47:53 +01:00
Robert O'Callahan 2ca28d964b Limit YOSYS_MAX_THREADS to 4 for abcopt-tests 2025-12-04 12:09:49 +01:00
Robert O'Callahan a871415abf Limit YOSYS_MAX_THREADS to 4 when running seed-tests 2025-12-04 12:09:48 +01:00
Robert O'Callahan fc951a28d3 Limit YOSYS_MAX_THREADS to 4 when running makefile-tests so we don't overload systems when running 'make -j... test' 2025-12-04 12:09:04 +01:00
Gus Smith 07a690570e
Merge pull request #5128 from gussmith23/gussmith23-rosette-backend-updates 
Add association-list-based helper functions into Rosette backend
 2025-12-02 16:27:05 -08:00
Emil J. Tywoniak 36f0e0392f aiger2: add crash test 2025-12-02 15:30:02 +01:00
Krystine Sherwin b2e527c67e
tests/aiger: Only write aigmap.err on error 2025-12-02 14:17:16 +13:00
Krystine Sherwin 6842003e76
tests/aiger: Add gold .aag files 
Generated with changes from 26f2c111
 2025-12-02 14:03:37 +13:00
Krystine Sherwin e2e7922756
tests/aiger: Compare .aag outputs against known 
Any files that differ (e.g. due to compiler order of operations changing) will trigger an error.
 2025-12-02 14:03:36 +13:00
Emil J 9871e9b17e
Merge pull request #5496 from YosysHQ/emil/liberty-flop-loops 
read_liberty: support loopy retention cells
 2025-12-01 22:50:20 +01:00
Gus Smith 38ee4fc730 Undo more unnecessary changes 2025-11-29 16:17:27 -08:00
Gus Smith 62e666c2ed Make run-test work from anywhere 2025-11-29 16:08:42 -08:00
Gus Smith fb8a1ad3bc Add back param 2025-11-29 16:07:18 -08:00
Gus Smith 0f8e1e3bf7 Undo more changes 2025-11-29 16:06:18 -08:00
Gus Smith 5f84b8b339 Undo some other changes 2025-11-29 15:32:19 -08:00
Gus Smith e223087578 Undo more changes that slipped in from somewhere? a merge maybe? 2025-11-29 15:28:34 -08:00
Gus Smith 5d5a7ab443 remove unused 2025-11-29 15:08:57 -08:00
Gus Smith 473edd19ed Undo formatting 2025-11-29 15:06:46 -08:00
Gus Smith 403740428c Remove unknown change 2025-11-29 15:01:17 -08:00
Gus Smith 6fe35fa46c Merge remote-tracking branch 'origin/main' into gussmith23-rosette-backend-updates 2025-11-29 14:20:36 -08:00
Natalia d4e0437cfd Fix Verific run-test.mk setup 2025-11-24 15:56:28 -08:00
Krystine Sherwin a8e8746fc0
tests: Tidy up bug3515 
Add base case where mapping is possible for sanity checking.
 2025-11-25 07:35:19 +13:00
Krystine Sherwin ba31a02578
tests: Add bug3515 2025-11-25 07:04:34 +13:00
Krystine Sherwin 44ab884b06 bug5495.sh: Skip test if timeout isn't available 2025-11-21 04:03:39 +00:00
Krystine Sherwin 4d1b688717
Tests: Add testcase for problematic ABC DONE check 2025-11-21 14:46:01 +13:00
Emil J. Tywoniak bfc957ee2d filterlib, read_liberty: add loopy retention cell formal equivalence test 2025-11-21 00:57:54 +01:00
Emil J. Tywoniak b3112bf025 filterlib: prefer using precedence over unsynthesizable verilog 2025-11-21 00:43:54 +01:00
Miodrag Milanović e83d721cb0
Merge pull request #5492 from donn/getitem 
pyosys: __getitem__ for supported classes
 2025-11-19 17:58:01 +01:00
Mohamed Gaber 58e831486d
pyosys: __getitem__ for supported classes 
- functions that have a const `[]` operator method now support `__getitem__` in Python
- fields of a pointer type now return a `reference_internal` instead of a `copy` because classes referenced to by pointers typically aren't copyable (e.g. RTLIL::Wire, RTLIL::Module, etc)
- removed duplicate of test_script.py
 2025-11-19 18:09:41 +02:00
Emil J. Tywoniak 920f4793fb sdc: error on unknown getters 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak 07de7509bf sdc: add -keep_hierarchy test 2025-11-19 15:26:02 +01:00
Emil J. Tywoniak dc48ceadd9 sdc: collect strictly matching objects 2025-11-19 15:25:24 +01:00
Emil J. Tywoniak c26aa3186d sdc: collect design objects 2025-11-19 15:25:24 +01:00
Miodrag Milanovic 58d4e2c38e ignore generated file 2025-11-17 13:35:38 +01:00
Robert O'Callahan b870693393 Fix reset_auto_counter_id to correctly detect _NNN_ patterns 
This fixes a regression caused by commit c4c389fdd7.
 2025-11-17 09:21:59 +00:00
Miodrag Milanović 4bfdc62f65
Merge pull request #5472 from Anhijkt/arst-fsm-handling 
fsm_detect: add adff detection
 2025-11-14 13:47:08 +01:00
Anhijkt b08195a9cf typo 2025-11-14 13:34:58 +02:00