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5021 Commits

Author SHA1 Message Date
Emil J. Tywoniak dda22a35d1 dfflibmap: deduplicate liberty cell search code 2026-07-14 10:44:00 +02:00
Iztok Jeras 94d10012e7 dfflibmap: picking first instead of last cell with smallest area 
In a standard cell library cells are usually ordered from weakest to strongest.
Sometimes the two weakest cells have the same area.
Previously the stroner (last) of the two was selected,
now the weaker (first is selected).
 2026-07-08 17:12:07 +02:00
Iztok Jeras 2d9876ccc4 dfflibmap: collected copies of the same code into a function 2026-07-08 17:12:07 +02:00
Iztok Jeras d0365d9e68 dfflibmap: simpler handling of cells with inverted data input polarity 2026-07-08 17:12:07 +02:00
Iztok Jeras bc133317f1 dfflibmap: recommend running opt_merge pass after dfflibmap 2026-07-08 17:12:07 +02:00
Iztok Jeras 143ffa08a1 dfflibmap: support for mapping latch cells 2026-07-08 17:12:07 +02:00
Iztok Jeras 109f442379 dfflegalize: make it explicit in the documentation, that the pass operates on FFs and LATCHes 2026-07-08 17:12:07 +02:00
Iztok Jeras fdea4e3722 documentation: avoid documentation rendering issue 2026-07-08 17:12:07 +02:00
nella 8dc32cbf4e
Merge pull request #6012 from YosysHQ/nella/fix-opt-reduce 
`opt_reduce`: restore pmux b-slice == a elim
 2026-07-08 13:36:04 +00:00
nella f6d810acf9 Restore pmux elim. 2026-07-08 11:58:30 +02:00
nella f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
Miodrag Milanovic 8ad4ffcdd1 Cleanup 2026-07-08 08:34:01 +02:00
nella 006cbc8f72
Merge pull request #5842 from YosysHQ/nella/opt_dff_elim_improvements 
opt_dff: Eliminate equivalent bits
 2026-07-06 12:02:50 +00:00
nella 0e56ca02ed Make opt_dff -sat conflict with -keepdc. 2026-07-06 13:47:10 +02:00
nella a3b8609c84 Add -nolatches check option. 2026-06-24 10:38:10 +02:00
Miodrag Milanovic fd3ec58055 Remove leftover use of log_id 2026-06-24 08:04:48 +02:00
KrystalDelusion a07c484ce1
Merge pull request #5981 from YosysHQ/krys/equiv_opt_unknown 
equiv_opt: Add ignore-unknown-cells
 2026-06-23 19:58:30 +00:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Krystine Sherwin de6aa77dc8
equiv_opt: Add ignore-unknown-cells 2026-06-23 10:54:00 +12:00
nella 3d0c868af0
Merge pull request #5952 from YosysHQ/nella/vector-index 
Optimize upto vector indexing (Fix #892).
 2026-06-22 09:05:26 +00:00
nella 6ffc938a75
Merge pull request #5701 from YosysHQ/gus/sim-with-vcd-tuneup 
Add warnings and errors to `sim -r` with VCD code path
 2026-06-22 09:02:32 +00:00
nella 2195277b5a
Merge pull request #5960 from YosysHQ/nella/latch-infer 
proc_dlatch - infer $adlatch (Fix #5910).
 2026-06-18 16:50:48 +00:00
nella c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745 
Fix  `chparam` values are unsigned when using read_verilog frontend
 2026-06-18 16:50:22 +00:00
nella b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella 32a268d745 Emit errors before dfflegalize. 2026-06-18 17:07:24 +02:00
nella 46cbeab720 Add effort limit. 2026-06-18 11:58:01 +02:00
nella 75a30a22d6 Cleanup bitsim, document hypo. 2026-06-18 11:43:13 +02:00
nella 25810193ab Reuse sat/hashlib. 2026-06-18 10:57:20 +02:00
nella a5bdb29d7f Recognise asynchronous set/reset. 2026-06-15 15:44:50 +02:00
nella 01e2698247 Add latch check step. 2026-06-15 15:09:23 +02:00
Emil J. Tywoniak 6032b064e2 opt_muxtree: optimize for single driver, error on multiple drivers 2026-06-15 15:08:26 +02:00
nella 7473fcf939 Add latch inference msg severity option. 2026-06-15 14:17:02 +02:00
nella 05805e8b93
Merge pull request #5900 from YosysHQ/nella/arith_tree_improvements 
arith_tree improvements
 2026-06-12 14:23:10 +00:00
nella 309b7d2496 Verify kogge stone impl. 2026-06-12 14:55:47 +02:00
nella 135c2a4113 Get rid of normalize_to_width. 2026-06-11 01:12:35 +02:00
nella d52670e58b Replace suitable (2^k-1)-x with ~x. 2026-06-10 11:29:55 +02:00
Lofty c96d7bc998
Merge pull request #5943 from YosysHQ/lofty/abc9-refactor-6 
move `abc9_ops -reintegrate` into its own pass
 2026-06-08 12:57:08 +00:00
nella c47ed4bc31 Fix help. 2026-06-08 13:47:56 +02:00
nella 3c6900a570 Depth-schedule finar adder. 2026-06-08 13:47:56 +02:00
nella f8d2252735 Use ripple as default final adder, gate fma. 2026-06-08 13:47:56 +02:00
nella d40431f249 Remove black boxes for now. 2026-06-08 13:29:05 +02:00
nella 5e4e5a1d40 Arith tree - parallel prefix. 2026-06-08 13:29:05 +02:00
nella 862e9fc54e Remove elarith-fast for now. 2026-06-08 13:29:05 +02:00
nella 25eb394ad0 Collapse signed*signed or combined nodes via BW. 2026-06-08 13:29:05 +02:00
nella bc07c6b1b0 Improve arith_tree: FMA add, elarith WIP. 2026-06-08 13:29:05 +02:00
Lofty 0e32ad7eed move abc9_ops -reintegrate into its own pass 2026-06-08 11:03:17 +01:00
Miodrag Milanovic 102f008194 Remove EMSCRIPTEN leftovers 2026-06-05 10:03:27 +02:00
Miodrag Milanović 693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize 
verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
 2026-06-04 05:43:04 +00:00
Miodrag Milanovic a599999d1f Fixed warnings found by gcc-16 2026-06-03 13:09:38 +02:00