mirror of https://github.com/YosysHQ/yosys.git
dfflibmap: support for mapping latch cells
This commit is contained in:
Iztok Jeras
parent
3fd01fcee9
commit
143ffa08a1
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@ -36,7 +36,7 @@ static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
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static void logmap(IdString dff)
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{
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if (cell_mappings.count(dff) == 0) {
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log(" unmapped dff cell: %s\n", dff);
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log(" unmapped dff/dlatch cell: %s\n", dff);
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} else {
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log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1));
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bool first = true;
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@ -80,6 +80,27 @@ static void logmap_all()
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logmap(ID($_DFFSR_PNP_));
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logmap(ID($_DFFSR_PPN_));
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logmap(ID($_DFFSR_PPP_));
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logmap(ID($_DLATCH_N_));
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logmap(ID($_DLATCH_P_));
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logmap(ID($_DLATCH_NN0_));
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logmap(ID($_DLATCH_NN1_));
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logmap(ID($_DLATCH_NP0_));
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logmap(ID($_DLATCH_NP1_));
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logmap(ID($_DLATCH_PN0_));
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logmap(ID($_DLATCH_PN1_));
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logmap(ID($_DLATCH_PP0_));
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logmap(ID($_DLATCH_PP1_));
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logmap(ID($_DLATCHSR_NNN_));
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logmap(ID($_DLATCHSR_NNP_));
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logmap(ID($_DLATCHSR_NPN_));
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logmap(ID($_DLATCHSR_NPP_));
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logmap(ID($_DLATCHSR_PNN_));
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logmap(ID($_DLATCHSR_PNP_));
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logmap(ID($_DLATCHSR_PPN_));
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logmap(ID($_DLATCHSR_PPP_));
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}
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static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std::string &data_name, bool &data_not_inverted, std::string &enable_name, bool &enable_not_inverted)
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@ -234,7 +255,7 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin
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return false;
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}
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static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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static void find_cell_dff(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool has_reset, bool rstpol, bool rstval, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -361,7 +382,7 @@ static void find_cell(std::vector<const LibertyAst *> cells, IdString cell_type,
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}
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}
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static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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static void find_cell_dffsr(std::vector<const LibertyAst *> cells, IdString cell_type, bool clkpol, bool setpol, bool clrpol, bool has_enable, bool enapol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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@ -493,9 +514,262 @@ static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_ty
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}
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}
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static void find_cell_dlatch(std::vector<const LibertyAst *> cells, IdString cell_type, bool enablepol, bool has_reset, bool rstpol, bool rstval, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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for (auto cell : cells)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *latch = cell->find("latch");
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if (latch == nullptr)
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continue;
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std::string cell_enable_pin, cell_rst_pin, cell_data_pin;
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bool cell_enable_pol, cell_rst_pol, cell_data_pol;
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if (!parse_pin(cell, latch->find("enable"), cell_enable_pin, cell_enable_pol) || cell_enable_pol != enablepol)
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continue;
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if (!parse_pin(cell, latch->find("data_in"), cell_data_pin, cell_data_pol))
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continue;
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if (has_reset && !cell_data_pol) {
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// data_in is negated
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// we later propagate this inversion to the output,
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// which requires the negation of the reset value
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rstval = !rstval;
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}
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if (has_reset && rstval == false) {
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if (!parse_pin(cell, latch->find("clear"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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if (has_reset && rstval == true) {
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if (!parse_pin(cell, latch->find("preset"), cell_rst_pin, cell_rst_pol) || cell_rst_pol != rstpol)
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continue;
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}
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_enable_pin] = 'E';
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if (has_reset)
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this_cell_ports[cell_rst_pin] = 'R';
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this_cell_ports[cell_data_pin] = 'D';
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == latch->args[0]) {
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this_cell_ports[pin->args[0]] = cell_data_pol ? 'Q' : 'q';
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if (cell_data_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == latch->args[1]) {
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this_cell_ports[pin->args[0]] = cell_data_pol ? 'q' : 'Q';
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if (!cell_data_pol)
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found_noninv_output = true;
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void find_cell_dlatchsr(std::vector<const LibertyAst *> cells, IdString cell_type, bool enablepol, bool setpol, bool clrpol, std::vector<std::string> &dont_use_cells)
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{
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const LibertyAst *best_cell = nullptr;
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std::map<std::string, char> best_cell_ports;
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int best_cell_pins = 0;
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bool best_cell_noninv = false;
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double best_cell_area = 0;
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for (auto cell : cells)
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{
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (std::string &dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *latch = cell->find("latch");
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if (latch == nullptr)
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continue;
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std::string cell_enable_pin, cell_set_pin, cell_clr_pin, cell_data_pin;
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bool cell_enable_pol, cell_set_pol, cell_clr_pol, cell_data_pol;
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if (!parse_pin(cell, latch->find("enable"), cell_enable_pin, cell_enable_pol) || cell_enable_pol != enablepol)
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continue;
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if (!parse_pin(cell, latch->find("data_in"), cell_data_pin, cell_data_pol))
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continue;
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if (!parse_pin(cell, latch->find("preset"), cell_set_pin, cell_set_pol))
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continue;
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if (!parse_pin(cell, latch->find("clear"), cell_clr_pin, cell_clr_pol))
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continue;
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if (!cell_data_pol) {
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// data_in is negated
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// we later propagate this inversion to the output,
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// which requires the swap of set and reset
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std::swap(cell_set_pin, cell_clr_pin);
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std::swap(cell_set_pol, cell_clr_pol);
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}
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if (cell_set_pol != setpol)
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continue;
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if (cell_clr_pol != clrpol)
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continue;
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std::map<std::string, char> this_cell_ports;
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this_cell_ports[cell_enable_pin] = 'E';
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this_cell_ports[cell_set_pin] = 'S';
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this_cell_ports[cell_clr_pin] = 'R';
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this_cell_ports[cell_data_pin] = 'D';
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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int num_pins = 0;
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bool found_output = false;
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bool found_noninv_output = false;
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for (auto pin : cell->children)
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{
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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const LibertyAst *dir = pin->find("direction");
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if (dir == nullptr || dir->value == "internal")
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continue;
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num_pins++;
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if (dir->value == "input" && this_cell_ports.count(pin->args[0]) == 0)
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goto continue_cell_loop;
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const LibertyAst *func = pin->find("function");
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if (dir->value == "output" && func != nullptr) {
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std::string value = func->value;
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for (size_t pos = value.find_first_of("\" \t"); pos != std::string::npos; pos = value.find_first_of("\" \t"))
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value.erase(pos, 1);
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if (value == latch->args[0]) {
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// next_state negation propagated to output
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this_cell_ports[pin->args[0]] = cell_data_pol ? 'Q' : 'q';
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if (cell_data_pol)
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found_noninv_output = true;
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found_output = true;
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} else
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if (value == latch->args[1]) {
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// next_state negation propagated to output
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this_cell_ports[pin->args[0]] = cell_data_pol ? 'q' : 'Q';
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if (!cell_data_pol)
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found_noninv_output = true;
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found_output = true;
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}
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}
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if (this_cell_ports.count(pin->args[0]) == 0)
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this_cell_ports[pin->args[0]] = 0;
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}
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if (!found_output || (best_cell != nullptr && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
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continue;
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if (best_cell != nullptr && num_pins == best_cell_pins && area > best_cell_area)
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continue;
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best_cell = cell;
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best_cell_pins = num_pins;
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best_cell_area = area;
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best_cell_noninv = found_noninv_output;
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best_cell_ports.swap(this_cell_ports);
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continue_cell_loop:;
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}
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if (best_cell != nullptr) {
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log(" cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
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best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
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cell_mappings[cell_type].cell_name = RTLIL::escape_id(best_cell->args[0]);
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cell_mappings[cell_type].ports = best_cell_ports;
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}
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}
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static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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{
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log("Mapping DFF cells in module `%s':\n", module->name);
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log("Mapping DFF/DLATCH cells in module `%s':\n", module->name);
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dict<SigBit, pool<Cell*>> notmap;
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SigMap sigmap(module);
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@ -568,19 +842,19 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
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}
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struct DfflibmapPass : public Pass {
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DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
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DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops and latches") { }
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void help() override
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{
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log("\n");
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log(" dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]\n");
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log("\n");
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log("Map internal flip-flop cells to the flip-flop cells in the technology\n");
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log("library specified in the given liberty files.\n");
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log("Map internal flip-flop/latch cells to the flip-flop/latch cells in the\n");
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log("technology library specified in the given liberty files.\n");
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log("\n");
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log("This pass may add inverters as needed. Therefore it is recommended to\n");
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log("first run this pass and then map the logic paths to the target technology.\n");
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log("\n");
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log("When called with -prepare, this command will convert the internal FF cells\n");
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log("When called with -prepare, this command will convert the internal FF/LATCH cells\n");
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log("to the internal cell types that best match the cells found in the given\n");
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log("liberty file, but won't actually map them to the target cells.\n");
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log("\n");
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@ -590,7 +864,7 @@ struct DfflibmapPass : public Pass {
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log("\n");
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log("When called with -info, this command will only print the target cell\n");
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log("list, along with their associated internal cell types, and the arguments\n");
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log("that would be passed to the dfflegalize pass. The design will not be\n");
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log("that would be passed to the dfflegalize pass. The design will not be\n");
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log("changed.\n");
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log("\n");
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log("When called with -dont_use, this command will not map to the specified cell\n");
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@ -601,7 +875,7 @@ struct DfflibmapPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
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log_header(design, "Executing DFFLIBMAP pass (mapping DFF/DLATCH cells to sequential cells from liberty file).\n");
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log_push();
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bool prepare_mode = false;
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@ -660,40 +934,65 @@ struct DfflibmapPass : public Pass {
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delete f;
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}
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find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
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// cells, cell_type , c_pol, has_r, r_pol, r_val, has_e, e_pol
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find_cell_dff(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);
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find_cell_dff(merged.cells, ID($_DFF_P_), true, false, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
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find_cell(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
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find_cell_dff(merged.cells, ID($_DFF_NN0_), false, true, false, false, false, false, dont_use_cells);
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find_cell_dff(merged.cells, ID($_DFF_NN1_), false, true, false, true, false, false, dont_use_cells);
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find_cell_dff(merged.cells, ID($_DFF_NP0_), false, true, true, false, false, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFF_NP1_), false, true, true, true, false, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFF_PN0_), true, true, false, false, false, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFF_PN1_), true, true, false, true, false, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFF_PP0_), true, true, true, false, false, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFF_PP1_), true, true, true, true, false, false, dont_use_cells);
|
||||
|
||||
find_cell(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
||||
find_cell(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFFE_NN_), false, false, false, false, true, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFFE_NP_), false, false, false, false, true, true, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFFE_PN_), true, false, false, false, true, false, dont_use_cells);
|
||||
find_cell_dff(merged.cells, ID($_DFFE_PP_), true, false, false, false, true, true, dont_use_cells);
|
||||
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
||||
find_cell_sr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
||||
// cells, cell_type , c_pol, s_pol, r_pol, has_e, e_pol
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_NNN_), false, false, false, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_NNP_), false, false, true, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_NPN_), false, true, false, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_NPP_), false, true, true, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_PNN_), true, false, false, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_PNP_), true, false, true, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_PPN_), true, true, false, false, false, dont_use_cells);
|
||||
find_cell_dffsr(merged.cells, ID($_DFFSR_PPP_), true, true, true, false, false, dont_use_cells);
|
||||
|
||||
log(" final dff cell mappings:\n");
|
||||
// cells, cell_type , e_pol, has_r, r_pol, r_val
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_N_), false, false, false, false, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_P_), true, false, false, false, dont_use_cells);
|
||||
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_NN0_), false, true, false, false, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_NN1_), false, true, false, true, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_NP0_), false, true, true, false, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_NP1_), false, true, true, true, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_PN0_), true, true, false, false, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_PN1_), true, true, false, true, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_PP0_), true, true, true, false, dont_use_cells);
|
||||
find_cell_dlatch(merged.cells, ID($_DLATCH_PP1_), true, true, true, true, dont_use_cells);
|
||||
|
||||
// cells, cell_type , e_pol, s_pol, r_pol
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_NNN_), false, false, false, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_NNP_), false, false, true, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_NPN_), false, true, false, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_NPP_), false, true, true, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_PNN_), true, false, false, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_PNP_), true, false, true, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_PPN_), true, true, false, dont_use_cells);
|
||||
find_cell_dlatchsr(merged.cells, ID($_DLATCHSR_PPP_), true, true, true, dont_use_cells);
|
||||
|
||||
log(" final dff/dlatch cell mappings:\n");
|
||||
logmap_all();
|
||||
|
||||
if (!map_only_mode) {
|
||||
std::string dfflegalize_cmd = "dfflegalize";
|
||||
for (auto it : cell_mappings)
|
||||
dfflegalize_cmd += stringf(" -cell %s 01", it.first);
|
||||
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
|
||||
dfflegalize_cmd += " t:$_DFF* t:$_SDFF* t:$_DLATCH*";
|
||||
if (info_mode) {
|
||||
log("dfflegalize command line: %s\n", dfflegalize_cmd);
|
||||
} else {
|
||||
|
|
|
|||
Loading…
Reference in New Issue