From 9d93aa275a0c4e9a0699d9f0751454dfe4444a9f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 26 Aug 2026 22:12:45 +0200 Subject: [PATCH] tests: ignore $input_port and $connect in cell counts --- tests/arch/ice40/ice40_opt.ys | 2 +- tests/memlib/generate_mk.py | 3 ++- tests/proc/yosys_latch.ys | 2 +- tests/various/muxcover.ys | 2 +- tests/various/peepopt.ys | 12 ++++++------ 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index e779ab207..5a7a39d30 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -24,7 +24,7 @@ EOT read_verilog -icells -lib +/ice40/abc9_model.v +/ice40/cells_sim.v equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt design -load postopt -select -assert-count 1 t:* +select -assert-count 1 t:* t:$*_port %d t:$public %d select -assert-count 1 t:$lut # https://github.com/YosysHQ/yosys/issues/1543 diff --git a/tests/memlib/generate_mk.py b/tests/memlib/generate_mk.py index 230d2ebd6..9de00df05 100644 --- a/tests/memlib/generate_mk.py +++ b/tests/memlib/generate_mk.py @@ -1566,7 +1566,8 @@ for t in TESTS: for kk, vv in ca.items(): sf.write("select -assert-count {} t:{} r:{}={} %i\n".format(cc, k, kk, vv)) else: - sf.write("select -assert-count {} t:{}\n".format(v, k)) + suffix = " t:$*_port %d t:$public %d" if k.startswith("$") else "" + sf.write("select -assert-count {} t:{}{}\n".format(v, k, suffix)) def create_tests(): for t in TESTS: diff --git a/tests/proc/yosys_latch.ys b/tests/proc/yosys_latch.ys index c60a5bc00..40e106029 100644 --- a/tests/proc/yosys_latch.ys +++ b/tests/proc/yosys_latch.ys @@ -13,7 +13,7 @@ select -assert-count 1 t:$_DLATCH_P_ select -assert-count 1 t:$_DLATCH_N_ select -assert-count 1 t:$_DLATCH_PN0_ select -assert-count 1 t:$_DLATCH_NN0_ -select -assert-count 4 t:* +select -assert-count 4 t:* t:$*_port %d t:$public %d design -load gold equiv_opt -assert -multiclock simplemap diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 37a90dcb0..5141af58c 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -539,7 +539,7 @@ simplemap t:\$mux muxcover opt_clean -purge select -assert-count 1 t:$_MUX8_ -select -assert-none t:$_MUX8_ %% t:* %D +select -assert-none t:$_MUX8_ %% t:* %D t:$*_port %d techmap -map +/simcells.v t:$_MUX8_ design -stash gate diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index e0b9946cf..ea81de6e0 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -9,7 +9,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$bmux -select -assert-count 0 t:$bmux t:* %D +select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d #################### @@ -26,7 +26,7 @@ design -load postopt clean select -assert-count 1 t:$shr select -assert-count 1 t:$mul -select -assert-count 0 t:$shr t:$mul %% t:* %D +select -assert-count 0 t:$shr t:$mul %% t:* %D t:$*_port %d t:$public %d #################### @@ -50,7 +50,7 @@ sat -verify -show-public -enable_undef -prove-asserts miter cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul -select -assert-count 0 t:$shr t:$mul %% t:* %D +select -assert-count 0 t:$shr t:$mul %% t:* %D t:$*_port %d t:$public %d #################### @@ -92,7 +92,7 @@ prep -nokeepdc equiv_opt -assert peepopt design -load postopt clean -select -assert-count 0 t:* +select -assert-count 0 t:* t:$*_port %d t:$public %d #################### @@ -109,7 +109,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$bmux -select -assert-count 0 t:$bmux t:* %D +select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d #################### @@ -244,4 +244,4 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$bmux -select -assert-count 0 t:$bmux t:* %D +select -assert-count 0 t:$bmux t:* %D t:$*_port %d t:$public %d