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design: reset twine pool when resetting current design

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This commit is contained in:
Emil J. Tywoniak
2026-10-02 18:42:02 +02:00
parent d5decad312
commit 950a53fd3c
1 changed files with 3 additions and 0 deletions
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passes/cmds/design.cc
+3
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@@ -371,6 +371,9 @@ struct DesignPass : public Pass {
design->verilog_defines->clear();
}
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
design->twines = TwinePool();
if (!load_name.empty() || pop_mode)
{
RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);