From 950a53fd3cf1efd2999e55a00b041e28cd869b35 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 1 Oct 2026 15:51:17 +0200
Subject: [PATCH] design: reset twine pool when resetting current design

---
 passes/cmds/design.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 0b6618f81..93a47a091 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -371,6 +371,9 @@ struct DesignPass : public Pass {
 			design->verilog_defines->clear();
 		}
 
+		if (reset_mode || !load_name.empty() || push_mode || pop_mode)
+			design->twines = TwinePool();
+
 		if (!load_name.empty() || pop_mode)
 		{
 			RTLIL::Design *saved_design = pop_mode ? pushed_designs.back() : saved_designs.at(load_name);