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xschem/xschem_library/logic
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Stefan Frederik 7f9ee9fc2a add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym 2021-11-21 12:28:36 +01:00
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bf.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
bf.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
eo.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
eo.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
ff.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
ff.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
iv.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
iv.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
latch.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
latch.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
nd2.sym cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator) 2020-10-13 02:52:37 +02:00
nr2.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
ram.sch fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion 2020-12-23 18:16:53 +01:00
ram.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
ram_tb.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
stimuli.test_ngspice populating xschem git repo 2020-08-08 15:47:34 +02:00
sync_reg.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
sync_reg.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
test_mos_verilog.sch add "xschem check_symbols" and "xschem reload_symbols" for future checking of symbols that are newer wrt to schematic. set mtime of newly created schematic (that does not exist on disk) to current time. Add verilog attributes to devices/pmos4.sym 2021-11-21 12:28:36 +01:00
test_mos_verilog.sym added test_mos_verilog.sym example in top schematic page 2021-11-21 00:53:37 +01:00
test_ngspice.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
test_ngspice.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
testbench.sch populating xschem git repo 2020-08-08 15:47:34 +02:00
testbench.sym populating xschem git repo 2020-08-08 15:47:34 +02:00