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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
1,781 Commits 3 Branches 10 Tags 86 MiB
C 71.5%
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stefan schippers ea533bd9e3 added bus_tap.sym 2023-05-21 23:59:50 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions