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*_ignore attributes for instances and symbols cached in .flags struct member for speed optimization. added some generator netlist testcases in xschemtest.tcl

This commit is contained in:
stefan schippers 2023-05-10 23:29:16 +02:00
parent 339c523f0b
commit 5e281e7f10
14 changed files with 238 additions and 179 deletions
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8
src/actions.c
View File

@ -1098,6 +1098,14 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
}
dbg(1, "place_symbol(): done set_inst_prop()\n"); /* 03-02-2000 */
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[n].flags |= SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[n].flags |= VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[n].flags |= VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[n].flags |= TEDAX_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"hide",0), "true"))
xctx->inst[n].flags |= HIDE_INST;
if(!strcmp(get_tok_value(xctx->inst[n].prop_ptr,"highlight",0), "true"))

22
src/draw.c
View File

@ -445,43 +445,43 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
(
xctx->netlist_type == CAD_SPICE_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "spice_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "spice_ignore", 0), "true")
(xctx->inst[n].flags & SPICE_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & SPICE_IGNORE_INST)
)
) ||
(
xctx->netlist_type == CAD_VERILOG_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "verilog_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "verilog_ignore", 0), "true")
(xctx->inst[n].flags & VERILOG_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & VERILOG_IGNORE_INST)
)
) ||
(
xctx->netlist_type == CAD_VHDL_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "vhdl_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "vhdl_ignore", 0), "true")
(xctx->inst[n].flags & VHDL_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & VHDL_IGNORE_INST)
)
) ||
(
xctx->netlist_type == CAD_TEDAX_NETLIST &&
(
!strcmp(get_tok_value(xctx->inst[n].prop_ptr, "tedax_ignore", 0), "true") ||
!strcmp(get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "tedax_ignore", 0), "true")
(xctx->inst[n].flags & TEDAX_IGNORE_INST) ||
(xctx->sym[xctx->inst[n].ptr].flags & TEDAX_IGNORE_INST)
)
)
) {
xctx->inst[n].flags |= 16; /* *_ignore=true */
xctx->inst[n].flags |= IGNORE_INST; /* *_IGNORE_INST in current netlisting mode as evaluated above */
} else {
xctx->inst[n].flags &= ~16;
xctx->inst[n].flags &= ~IGNORE_INST;
}
}
}
if(xctx->inst[n].flags & 16) {
if(xctx->inst[n].flags & IGNORE_INST) {
c = GRIDLAYER;
what = NOW;
disabled = 1;

25
src/editprop.c
View File

@ -1392,11 +1392,28 @@ static void update_symbol(const char *result, int x)
get_tok_value(xctx->inst[*ii].prop_ptr, "lab",0));
}
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"highlight",0), "true"))
xctx->inst[*ii].flags |= HILIGHT_CONN;
else xctx->inst[*ii].flags &= ~HILIGHT_CONN;
xctx->inst[*ii].flags |= HILIGHT_CONN;
else xctx->inst[*ii].flags &= ~HILIGHT_CONN;
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[*ii].flags |= SPICE_IGNORE_INST;
else xctx->inst[*ii].flags &= ~SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[*ii].flags |= VERILOG_IGNORE_INST;
else xctx->inst[*ii].flags &= ~VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[*ii].flags |= VHDL_IGNORE_INST;
else xctx->inst[*ii].flags &= ~VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[*ii].flags |= TEDAX_IGNORE_INST;
else xctx->inst[*ii].flags &= ~TEDAX_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[*ii].prop_ptr,"hide",0), "true"))
xctx->inst[*ii].flags |= HIDE_INST;
else xctx->inst[*ii].flags &= ~HIDE_INST;
xctx->inst[*ii].flags |= HIDE_INST;
else xctx->inst[*ii].flags &= ~HIDE_INST;
xctx->inst[*ii].embed = !strcmp(get_tok_value(xctx->inst[*ii].prop_ptr, "embed", 2), "true");
} /* end for(k=0;k<xctx->lastsel; ++k) */

12
src/netlist.c
View File

@ -954,14 +954,10 @@ static int name_nodes_of_pins_labels_and_propagate()
if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */
if(for_netlist>0) {
/* 20150918 skip labels / pins if ignore property specified on instance */
if( xctx->netlist_type == CAD_VERILOG_NETLIST &&
strcmp(get_tok_value(inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if( xctx->netlist_type == CAD_SPICE_NETLIST &&
strcmp(get_tok_value(inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if( xctx->netlist_type == CAD_VHDL_NETLIST &&
strcmp(get_tok_value(inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if( xctx->netlist_type == CAD_TEDAX_NETLIST &&
strcmp(get_tok_value(inst[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
if( xctx->netlist_type == CAD_VERILOG_NETLIST && (inst[i].flags & VERILOG_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_SPICE_NETLIST && (inst[i].flags & SPICE_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_VHDL_NETLIST && (inst[i].flags & VHDL_IGNORE_INST)) continue;
if( xctx->netlist_type == CAD_TEDAX_NETLIST && (inst[i].flags & TEDAX_IGNORE_INST)) continue;
}
port=0;
my_strdup2(_ALLOC_ID_, &dir, "");

11
src/paste.c
View File

@ -283,8 +283,19 @@ static void merge_inst(int k,FILE *fd)
/* new_prop_string() for cleaning some internal caches. */
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"hide",0), "true"))
xctx->inst[i].flags |= HIDE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"highlight",0), "true"))
xctx->inst[i].flags |= HILIGHT_CONN;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[i].flags |= SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[i].flags |= VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[i].flags |= VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[i].flags |= TEDAX_IGNORE_INST;
xctx->inst[i].embed = !strcmp(get_tok_value(xctx->inst[i].prop_ptr, "embed", 2), "true");
my_free(_ALLOC_ID_, &prop_ptr);
xctx->instances++;

41
src/save.c
View File

@ -1899,6 +1899,16 @@ static void load_inst(int k, FILE *fd)
my_strdup2(_ALLOC_ID_, &xctx->inst[i].instname, get_tok_value(xctx->inst[i].prop_ptr, "name", 0));
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"hide",0), "true"))
xctx->inst[i].flags |= HIDE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[i].flags |= SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[i].flags |= VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[i].flags |= VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[i].flags |= TEDAX_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"highlight",0), "true"))
xctx->inst[i].flags |= HILIGHT_CONN;
@ -3297,6 +3307,21 @@ int load_sym_def(const char *name, FILE *embed_fd)
symbol[symbols].flags |= HIDE_INST;
else symbol[symbols].flags &= ~HIDE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"spice_ignore",0), "true"))
symbol[symbols].flags |= SPICE_IGNORE_INST;
else symbol[symbols].flags &= ~SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"verilog_ignore",0), "true"))
symbol[symbols].flags |= VERILOG_IGNORE_INST;
else symbol[symbols].flags &= ~VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"vhdl_ignore",0), "true"))
symbol[symbols].flags |= VHDL_IGNORE_INST;
else symbol[symbols].flags &= ~VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"tedax_ignore",0), "true"))
symbol[symbols].flags |= TEDAX_IGNORE_INST;
else symbol[symbols].flags &= ~TEDAX_IGNORE_INST;
}
else {
load_ascii_string(&aux_ptr, lcc[level].fd);
@ -3316,6 +3341,22 @@ int load_sym_def(const char *name, FILE *embed_fd)
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"hide",0), "true"))
symbol[symbols].flags |= HIDE_INST;
else symbol[symbols].flags &= ~HIDE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"spice_ignore",0), "true"))
symbol[symbols].flags |= SPICE_IGNORE_INST;
else symbol[symbols].flags &= ~SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"verilog_ignore",0), "true"))
symbol[symbols].flags |= VERILOG_IGNORE_INST;
else symbol[symbols].flags &= ~VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"vhdl_ignore",0), "true"))
symbol[symbols].flags |= VHDL_IGNORE_INST;
else symbol[symbols].flags &= ~VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(symbol[symbols].prop_ptr,"tedax_ignore",0), "true"))
symbol[symbols].flags |= TEDAX_IGNORE_INST;
else symbol[symbols].flags &= ~TEDAX_IGNORE_INST;
}
else {
load_ascii_string(&aux_ptr, lcc[level].fd);

35
src/scheduler.c
View File

@ -3345,9 +3345,27 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"highlight",0), "true"))
xctx->inst[inst].flags |= HILIGHT_CONN;
else xctx->inst[inst].flags &= ~HILIGHT_CONN;
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"hide",0), "true"))
xctx->inst[inst].flags |= HIDE_INST;
else xctx->inst[inst].flags &= ~HIDE_INST;
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[inst].flags |= SPICE_IGNORE_INST;
else xctx->inst[inst].flags &= ~SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[inst].flags |= VERILOG_IGNORE_INST;
else xctx->inst[inst].flags &= ~VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[inst].flags |= VHDL_IGNORE_INST;
else xctx->inst[inst].flags &= ~VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[inst].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[inst].flags |= TEDAX_IGNORE_INST;
else xctx->inst[inst].flags &= ~TEDAX_IGNORE_INST;
xctx->inst[inst].embed = !strcmp(get_tok_value(xctx->inst[inst].prop_ptr, "embed", 2), "true");
if(!fast) {
/* new symbol bbox after prop changes (may change due to text length) */
@ -3699,6 +3717,23 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
} else {
my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, "true"));
}
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0), "true"))
xctx->inst[i].flags |= SPICE_IGNORE_INST;
else xctx->inst[i].flags &= ~SPICE_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0), "true"))
xctx->inst[i].flags |= VERILOG_IGNORE_INST;
else xctx->inst[i].flags &= ~VERILOG_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0), "true"))
xctx->inst[i].flags |= VHDL_IGNORE_INST;
else xctx->inst[i].flags &= ~VHDL_IGNORE_INST;
if(!strcmp(get_tok_value(xctx->inst[i].prop_ptr,"tedax_ignore",0), "true"))
xctx->inst[i].flags |= TEDAX_IGNORE_INST;
else xctx->inst[i].flags &= ~TEDAX_IGNORE_INST;
set_modify(1);
}
}

38
src/spice_netlist.c
View File

@ -163,11 +163,9 @@ static int spice_netlist(FILE *fd, int spice_stop )
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
if(top_sub && !flag) {
@ -188,11 +186,9 @@ static int spice_netlist(FILE *fd, int spice_stop )
if(top_sub) fprintf(fd, "\n");
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -282,11 +278,9 @@ int global_spice_netlist(int global) /* netlister driver */
first = 0;
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=header' property */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -315,11 +309,9 @@ int global_spice_netlist(int global) /* netlister driver */
/* print top subckt ipin/opins */
for(i=0;i<xctx->instances; ++i) {
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
dbg(1, "global_spice_netlist(): |%s|\n", type);
/*
@ -341,11 +333,9 @@ int global_spice_netlist(int global) /* netlister driver */
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
and no place=header */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -412,7 +402,7 @@ int global_spice_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->sym[i].flags & SPICE_IGNORE_INST) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@ -465,11 +455,9 @@ int global_spice_netlist(int global) /* netlister driver */
if(!split_f) {
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=end' property */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "spice_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & SPICE_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & SPICE_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {

14
src/tedax_netlist.c
View File

@ -35,11 +35,9 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
if(!tedax_stop) {
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "tedax_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & TEDAX_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & TEDAX_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
print_tedax_element(fd, i) ; /* this is the element line */
@ -47,11 +45,9 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
}
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "tedax_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & TEDAX_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & TEDAX_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -207,7 +203,7 @@ int global_tedax_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"tedax_ignore",0),"true")==0 ) continue;
if(xctx->sym[i].flags & TEDAX_IGNORE_INST) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))

63
src/verilog_netlist.c
View File

@ -43,12 +43,9 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
dbg(2, "verilog_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -131,11 +128,9 @@ int global_verilog_netlist(int global) /* netlister driver */
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -165,11 +160,9 @@ int global_verilog_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -183,11 +176,9 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -233,11 +224,9 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level out pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -256,11 +245,9 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -279,11 +266,9 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -305,11 +290,9 @@ int global_verilog_netlist(int global) /* netlister driver */
fprintf(fd,"---- begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -360,7 +343,7 @@ int global_verilog_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->sym[i].flags & VERILOG_IGNORE_INST) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path)) {
@ -479,11 +462,9 @@ int verilog_block_netlist(FILE *fd, int i)
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(j=0;j<xctx->instances; ++j)
{
if( strcmp(get_tok_value(xctx->inst[j].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[j].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[j].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[j].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[j].ptr].flags & VERILOG_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -583,11 +564,9 @@ int verilog_block_netlist(FILE *fd, int i)
err |= verilog_netlist(fd, verilog_stop);
fprintf(fd,"---- begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "verilog_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VERILOG_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VERILOG_IGNORE_INST) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

100
src/vhdl_netlist.c
View File

@ -39,12 +39,10 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user declarations\n");
for(l=0;l<xctx->instances; ++l)
{
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
if(!strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "arch_declarations") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr? xctx->inst[l].prop_ptr: "");
}
@ -58,11 +56,9 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"attributes"))==0)
{
@ -77,11 +73,9 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{ /* dont print elements with vhdl_ignore=true set in symbol */
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
dbg(2, "vhdl_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
@ -162,13 +156,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level packages\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"package"))==0)
{
@ -183,11 +173,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level use statements\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"use"))==0)
{
@ -252,11 +240,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -273,11 +259,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -294,11 +278,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -316,11 +298,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level port attributes\n");
for(i=0;i<xctx->instances; ++i)
{
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -340,7 +320,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
for(j=0;j<xctx->symbols; ++j)
{
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->sym[j].flags & VHDL_IGNORE_INST) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[j].name), ""));
@ -398,11 +378,9 @@ int global_vhdl_netlist(int global) /* netlister driver */
fprintf(fd,"//// begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[i].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[i].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[i].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[i].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -453,7 +431,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->sym[i].flags & VHDL_IGNORE_INST) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@ -564,12 +542,10 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances; ++l)
{
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
}
@ -577,12 +553,10 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): use statements\n");
for(l=0;l<xctx->instances; ++l)
{
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
}
@ -623,11 +597,9 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): port attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -662,11 +634,9 @@ int vhdl_block_netlist(FILE *fd, int i)
found=0;
for(l=0;l<xctx->instances; ++l)
{
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
if(!xctx->x_strcmp(xctx->sym[j].name, tcl_hook2(xctx->inst[l].name)))
{
found=1; break;
@ -712,11 +682,9 @@ int vhdl_block_netlist(FILE *fd, int i)
fprintf(fd,"//// begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"vhdl_ignore",0),"true")==0 ) continue;
if(xctx->inst[l].ptr<0) continue;
if(!strcmp(get_tok_value( (xctx->inst[l].ptr+ xctx->sym)->prop_ptr, "vhdl_ignore",0 ), "true") ) {
continue;
}
if(xctx->inst[l].flags & VHDL_IGNORE_INST) continue;
if(xctx->sym[xctx->inst[l].ptr].flags & VHDL_IGNORE_INST) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

21
src/xschem.h
View File

@ -170,6 +170,11 @@ extern char win_temp_dir[PATH_MAX];
#define EMBEDDED 1 /* used for embedded symbols marking in Symbol.flags */
#define HILIGHT_CONN 4 /* used to hilight instances if connected wire is hilighted */
#define HIDE_INST 8 /* will only show a bounding box for specific symbol instance */
#define SPICE_IGNORE_INST 16
#define VERILOG_IGNORE_INST 32
#define VHDL_IGNORE_INST 64
#define TEDAX_IGNORE_INST 128
#define IGNORE_INST 256
#define CADMAXGRIDPOINTS 512
#define CADMAXHIER 80
#define CADCHUNKALLOC 512 /* was 256 20102004 */
@ -520,7 +525,14 @@ typedef struct
char *templ;
int flags; /* bit 0: embedded flag
* bit 1: **free**
* bit 2: highight if connected wire highlighted */
* bit 2: highight if connected wire highlighted
* bit 4: spice_ignore=true
* bit 5: verilog_ignore=true
* bit 6: vhdl_ignore=true
* bit 7: tedax_ignore=true
* bit 8: instance must be ignored based on *_ignore=true and netlisting mode. used in draw.c
*/
} xSymbol;
typedef struct
@ -547,7 +559,12 @@ typedef struct
* 1: ordinary symbol, 0: label/pin/show
* bit 2: highlight if connected net/label is highlighted
* bit 3: hidden instance, show only bounding box (hide=true attribute)
* bit 4: disabled instance (*_ignore=true), will draw in grey */
* bit 4: spice_ignore=true
* bit 5: verilog_ignore=true
* bit 6: vhdl_ignore=true
* bit 7: tedax_ignore=true
* bit 8: instance must be ignored based on *_ignore=true and netlisting mode. used in draw.c
*/
char *prop_ptr;
char **node;
char *lab; /* lab attribute if any (pin/label) */

3
tests/xschemtest.tcl
View File

@ -200,6 +200,9 @@ proc netlist_test {} {
pcb_test1.sch tedax 1925087189
test_doublepin.sch spice 64707104
simulate_ff.sch spice 1321596936
test_symbolgen.sch spice 486085716
inst_sch_select.sch spice 695251894
test_mosgen.sch spice 21996225
} {
xschem set netlist_type $t
xschem load [abs_sym_path $f]

24
xschem_library/examples/0_examples_top.sch
View File

@ -70,7 +70,7 @@ T {Arcs/Circles} 960 -240 0 0 0.6 0.6 {layer=4}
T {Select the components here under
and press'<Ctrl>-h' or <Ctrl>-click
them to visit xschem websites
or local docs} 400 -310 0 0 0.3 0.3 {slant=oblique }
or local docs} 400 -290 0 0 0.3 0.3 {slant=oblique }
T {SPECIAL OBJECTS} 1220 -840 0 0 0.6 0.6 {layer=7}
T {Embedded
PNG
@ -81,14 +81,14 @@ that's me...)
T {Simulation
Graphs
} 1530 -550 0 0 0.6 0.6 {layer=4}
T {Bus rippers} 580 -400 0 0 0.6 0.6 {layer=4}
T {Bus rippers} 580 -380 0 0 0.6 0.6 {layer=4}
N 820 -420 940 -420 {lab=#net1}
N 860 -460 860 -370 {lab=#net2}
N 860 -390 920 -390 {lab=#net2}
N 880 -430 910 -420 {lab=#net1}
N 380 -330 640 -330 {lab=BUS[4:0]}
N 510 -420 510 -340 {lab=BUS[1]}
N 410 -380 410 -340 {lab=BUS[2]}
N 380 -310 640 -310 {lab=BUS[4:0]}
N 510 -400 510 -320 {lab=BUS[1]}
N 410 -360 410 -320 {lab=BUS[2]}
C {poweramp.sym} 480 -690 0 0 {name=x1
tclcommand="xschem descend"}
C {tesla.sym} 160 -570 0 0 {name=x2}
@ -100,26 +100,26 @@ C {cmos_example.sym} 160 -650 0 0 {name=x6}
C {greycnt.sym} 160 -690 0 0 {name=x8}
C {loading.sym} 160 -730 0 0 {name=x9}
C {inv_bsource.sym} 880 -320 0 0 {name=B1 TABLE="1.4 3.0 1.6 0.0"}
C {launcher.sym} 460 -160 0 0 {name=h1
C {launcher.sym} 460 -140 0 0 {name=h1
descr="XSCHEM ON REPO.HU"
url="http://repo.hu/projects/xschem"
program=x-www-browser}
C {launcher.sym} 460 -110 0 0 {name=h3
C {launcher.sym} 460 -90 0 0 {name=h3
descr="Toggle light/dark
colorscheme"
tclcommand="xschem toggle_colorscheme"
}
C {launcher.sym} 460 -210 0 0 {name=h2
C {launcher.sym} 460 -190 0 0 {name=h2
descr="LOCAL DOCUMENTATION"
url="$\{XSCHEM_SHAREDIR\}/../doc/xschem/index.html"
program=x-www-browser
}
C {rlc.sym} 160 -770 0 0 {name=x0}
C {lab_pin.sym} 640 -330 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
C {bus_connect.sym} 500 -330 0 0 {name=l3 lab=BUS[1]}
C {bus_connect_nolab.sym} 400 -330 0 0 {name=r1}
C {lab_pin.sym} 410 -380 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {lab_pin.sym} 640 -310 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
C {bus_connect.sym} 500 -310 0 0 {name=l3 lab=BUS[1]}
C {bus_connect_nolab.sym} 400 -310 0 0 {name=r1}
C {lab_pin.sym} 410 -360 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
C {LCC_instances.sym} 160 -450 0 0 {name=x7}
C {test_backannotated_subckt.sym} 160 -410 0 0 {name=x10}
C {plot_manipulation.sym} 160 -370 0 0 {name=x11}