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bf.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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bf.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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eo.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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eo.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ff.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ff.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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iv.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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iv.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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latch.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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latch.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nd2.sym
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cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator)
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2020-10-13 02:52:37 +02:00 |
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nr2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ram.sch
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Doc updates (sim_pinnumber), example circuits update
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2022-10-17 12:45:48 +02:00 |
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ram.sym
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Doc updates (sim_pinnumber), example circuits update
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2022-10-17 12:45:48 +02:00 |
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ram_tb.sch
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better check for availability of -justify option in listboxes
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2022-05-29 00:36:19 +02:00 |
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stimuli.test_ngspice
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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sync_reg.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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sync_reg.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test_mos_verilog.sch
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removed comment in schematic test_verilog_verilog.sch
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2021-12-01 15:58:26 +01:00 |
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test_mos_verilog.sym
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added test_mos_verilog.sym example in top schematic page
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2021-11-21 00:53:37 +01:00 |
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test_ngspice.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test_ngspice.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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testbench.sch
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better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates.
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2022-10-20 20:25:49 +02:00 |
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testbench.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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