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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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stefan schippers e26e03ff0b comments on top of change_sch_path() 2024-11-03 00:23:49 +01:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin proc ev, ev0, to_eng: evaluate expr at global scope so global vars will be expanded correctly ($path) 2024-05-29 09:41:52 +02:00
doc update docs: cph() continuous phase graph function 2024-10-18 02:30:47 +02:00
scconfig fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable) 2024-08-28 09:39:43 +02:00
src comments on top of change_sch_path() 2024-11-03 00:23:49 +01:00
tests update hash calculation in xschemtest.tcl for LCC_instances netlist (due to changes in schematic) 2024-09-10 22:38:44 +02:00
xschem_library added ngspice/tb_diff_amp.sch Verilog-A example 2024-10-30 16:10:17 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions