fix escape recognition in translate3(), so in symbol texts it is possible to write \\@name to an instance attribute to get literal @name in displayed text instead of the instance name. fix typo in tutorial_use_existing_subckt.html. some schematic updates (no more enable show_pin_net_names tcl variable)
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4f0c3afa23
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a725838850
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@ -122,7 +122,7 @@ format="@name @pinlist @symname"
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<pre class="code">
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format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname"
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</pre>
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</p>
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<p>
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In this case you specify the port order one by one explicitly. This can be used for spice
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primitive devices, spice subcircuits (like this example), VHDL and Verilog primitives.
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This method can NOT be used for VHDL and verilog subcircuits since for these you
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@ -134,7 +134,7 @@ format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname"
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</li>
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<a id="spice_sym_def">
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<a id="spice_sym_def"></a>
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<li>
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<h3> Obtaining the pin ordering from the subcircuit definition specified via <kbd>spice_sym_def</kbd></h3>
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<p>
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@ -183,7 +183,6 @@ x1 XZ XVCC XVSS XA XB XC symbol_include
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</li>
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</a>
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@ -201,6 +201,7 @@ static char *readq(FILE *f, char *str, long strmax, int quote, int do_esc, int *
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}
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/* get the next chunk */
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*str = '\0';
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fgets(str, strmax, f);
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}
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@ -768,9 +768,10 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
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#endif
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my_strdup2(_ALLOC_ID_, &txtptr, translate(n, text.txt_ptr));
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/* do another round of substitutions if some @var are found, but if not found leave @var as is */
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my_strdup2(_ALLOC_ID_, &txtptr, translate3(txtptr, 0, xctx->inst[n].prop_ptr,
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xctx->sym[xctx->inst[n].ptr].templ, NULL ));
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dbg(1, "drawing string: str=%s prop=%s\n", txtptr, text.prop_ptr ? text.prop_ptr : "NULL");
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my_strdup2(_ALLOC_ID_, &txtptr, translate3(txtptr, 1, xctx->inst[n].prop_ptr,
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xctx->sym[xctx->inst[n].ptr].templ, NULL ));
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dbg(1, "after translate3: str=%s\n", txtptr);
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draw_string(textlayer, what, txtptr,
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(text.rot + ( (flip && (text.rot & 1) ) ? rot+2 : rot) ) & 0x3,
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flip^text.flip, text.hcenter, text.vcenter,
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@ -4427,11 +4427,12 @@ const char *translate3(const char *s, int eat_escapes, const char *s1, const cha
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while(1) {
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c=*s++;
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if(c=='\\') {
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escape=1;
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if(eat_escapes) c=*s++;
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}
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else escape=0;
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space=SPACE(c);
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if( state==TOK_BEGIN && (c=='@' || c=='%' ) && !escape ) state=TOK_TOKEN; /* 20161210 escape */
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else if(state==TOK_TOKEN && token_pos > 1 &&
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@ -4441,6 +4442,8 @@ const char *translate3(const char *s, int eat_escapes, const char *s1, const cha
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)
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) state=TOK_SEP;
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if( c != '\\' && escape ) escape = 0;
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STR_ALLOC(&token, token_pos, &sizetok);
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if(state==TOK_TOKEN) token[token_pos++]=(char)c;
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else if(state==TOK_SEP) {
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@ -26,8 +26,6 @@ S {}
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E {}
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L 7 980 -150 1160 -150 {}
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P 4 7 210 -290 210 -370 220 -370 210 -390 200 -370 210 -370 210 -290 {}
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T {Title symbol has embedded TCL command
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to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7}
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T {Set tcl variable lvs_ignore to:
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- 1 to short elements with lvs_ignore=short attribute set
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to disable elements with lvs_ignore=open attribute set
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@ -76,14 +74,7 @@ lab=STARTUP}
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N 550 -520 700 -520 {
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lab=STARTUP}
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C {title.sym} 160 -30 0 0 {name=l1
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author="tcleval([
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if \{$show_pin_net_names == 0\} \{
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set lvs_ignore 0
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set show_pin_net_names 1
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xschem update_all_sym_bboxes
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\}
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return \{Stefan Schippers\}
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])"
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author="Stefan Schippers"
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}
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C {launcher.sym} 750 -90 0 0 {name=h1
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descr="Toggle lvs_ignore variable and
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@ -27,8 +27,6 @@ E {}
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L 7 930 -250 1110 -250 {}
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P 4 7 330 -690 330 -610 320 -610 330 -590 340 -610 330 -610 330 -690 {}
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P 4 7 650 -600 600 -600 600 -610 580 -600 600 -590 600 -600 650 -600 {}
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T {Title symbol has embedded TCL command
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to enable show_pin_net_names.} 160 -120 0 0 0.4 0.4 { layer=6}
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T {Set tcl variable IGNORE to 1 or 0 to
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enable / disable / short some components} 50 -940 0 0 1 1 {}
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T {tcleval(IGNORE=$IGNORE)} 930 -290 0 0 0.6 0.6 {name=l1}
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@ -47,41 +45,41 @@ depending on IGNORE} 1310 -540 0 0 0.4 0.4 { layer=1}
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N 130 -290 180 -290 {
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lab=NET_A}
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N 480 -290 530 -290 {
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lab=NET_A}
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lab=NET_B}
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N 180 -390 180 -290 {
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lab=NET_A}
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N 480 -390 480 -290 {
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lab=NET_A}
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lab=NET_B}
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N 180 -390 300 -390 {
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lab=NET_A}
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N 360 -390 480 -390 {
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lab=NET_A}
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lab=NET_B}
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N 160 -480 180 -480 {
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lab=NET_D}
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lab=NET_C}
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N 480 -480 530 -480 {
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lab=#net1}
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lab=NET_C}
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N 180 -580 180 -480 {
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lab=NET_D}
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lab=NET_C}
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N 480 -580 480 -480 {
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lab=#net1}
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lab=NET_C}
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N 180 -580 300 -580 {
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lab=NET_D}
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lab=NET_C}
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N 360 -580 480 -580 {
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lab=#net1}
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lab=NET_C}
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N 380 -480 480 -480 {
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lab=#net1}
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lab=NET_C}
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N 180 -480 300 -480 {
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lab=NET_D}
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lab=NET_C}
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N 380 -290 480 -290 {
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lab=NET_A}
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lab=NET_B}
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N 180 -290 300 -290 {
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lab=NET_A}
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N 610 -480 660 -480 {
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lab=NET_E}
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lab=#net1}
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N 660 -460 660 -400 {
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lab=NET_E}
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lab=#net1}
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N 660 -400 750 -400 {
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lab=NET_E}
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lab=#net1}
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N 660 -360 750 -360 {
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lab=NET_B}
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N 660 -360 660 -290 {
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@ -91,21 +89,21 @@ lab=NET_B}
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N 980 -380 1020 -380 {
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lab=NET_E}
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N 660 -460 760 -460 {
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lab=NET_E}
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lab=#net1}
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N 820 -460 980 -460 {
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lab=NET_E}
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N 980 -460 980 -380 {
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lab=NET_E}
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N 660 -480 660 -460 {
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lab=NET_E}
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lab=#net1}
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N 120 -420 160 -420 {
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lab=NET_D}
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lab=NET_C}
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N 160 -480 160 -420 {
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lab=NET_D}
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lab=NET_C}
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N 1560 -590 1680 -590 {
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lab=NET_B}
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lab=#net2}
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N 120 -480 160 -480 {
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lab=NET_D}
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lab=NET_C}
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N 1760 -590 1820 -590 {
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lab=NET_F}
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N 1210 -590 1480 -590 {
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@ -115,14 +113,7 @@ lab=NET_E}
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C {lab_pin.sym} 130 -290 0 0 {name=p3 sig_type=std_logic lab=NET_A}
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C {ipin.sym} 100 -190 0 0 { name=p4 lab=NET_D }
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C {title.sym} 160 -30 0 0 {name=l1
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author="tcleval([
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if \{$show_pin_net_names == 0\} \{
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set IGNORE 1
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set show_pin_net_names 1
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xschem update_all_sym_bboxes
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\}
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return \{Stefan Schippers\}
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])"
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author="Stefan Schippers"
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}
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C {short.sym} 330 -390 1 0 {name=x2
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spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -38,8 +38,6 @@ it becomes a short} 720 -410 0 0 0.4 0.4 { layer=4}
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T {Tier generator (tier.tcl)
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if 'lab' matches VDD | VCC | VPP shows
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as supply node, else show as ground node} 240 -640 0 0 0.4 0.4 { layer=4}
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T {Title symbol has embedded TCL command
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to enable show_pin_net_names.} 160 -120 0 0 0.4 0.4 { layer=6}
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N 180 -300 180 -240 {
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lab=VSS}
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N 180 -480 180 -360 {
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@ -94,11 +92,5 @@ tclcommand="edit_file [abs_sym_path res.tcl]"
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C {lab_show.sym} 460 -290 0 0 {name=l3}
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C {lab_show.sym} 570 -290 0 0 {name=l4}
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C {title.sym} 160 -30 0 0 {name=l5
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author="tcleval([
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if \{$show_pin_net_names == 0\} \{
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set show_pin_net_names 1
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xschem update_all_sym_bboxes
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\}
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return \{Stefan Schippers\}
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])"
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author="Stefan Schippers"
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}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -39,4 +39,4 @@ A 4 5 0 30 270 180 {}
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T {@name} -16.25 -5 0 0 0.2 0.2 {}
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T {@#1:net_name} -22.5 -17.5 0 1 0.15 0.15 {layer=15}
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T {@#0:net_name} 35 1.25 0 0 0.15 0.15 {layer=15}
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T {@#3:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}
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T {@#2:net_name} -22.5 22.5 0 1 0.15 0.15 {layer=15}
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