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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
2,815 Commits 3 Branches 10 Tags 88 MiB
C 71.5%
Tcl 15.7%
Awk 8.2%
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stefan schippers d656d4198a update hash netlist value in xschemtest.tcl for rom8k.sch 2024-07-18 22:09:25 +02:00
.github/workflows Configure github CI 2023-05-06 02:04:30 +02:00
XSchemWin proc ev, ev0, to_eng: evaluate expr at global scope so global vars will be expanded correctly ($path) 2024-05-29 09:41:52 +02:00
doc add `xschem log_write text` command so erc error messages are written into errfp instead of stderr by tcl 2024-07-12 07:09:32 +02:00
scconfig allow @symname , @param (param defined in symbol template string) translation in instance or symbol spice_sym_def attributes 2024-06-14 08:21:43 +02:00
src add `xschem log_write text` command so erc error messages are written into errfp instead of stderr by tcl 2024-07-12 07:09:32 +02:00
tests update hash netlist value in xschemtest.tcl for rom8k.sch 2024-07-18 22:09:25 +02:00
xschem_library small changes (typos) in autozero_comp.sch 2024-07-14 08:43:41 +02:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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Makefile added install_pdf to create pdf doc from html man pages 2023-07-03 11:38:09 +02:00
Makefile.conf.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in config.h: generate HAS_LIBREADLINE, do not add #include line for libreadline (yet) as this is wip 2024-05-01 11:53:54 +02:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions