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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Frederik ca8ffafe8a code refactoring (update_conn_cues()) 2022-11-07 14:23:57 +01:00
XSchemWin (JL) update abs_sym_path such that using network drive (ie. //192.168.1.102/test) will return as is, (JL) add example for network drive to add to XSCHEM_LIBRARY_PATH 2022-10-31 23:48:34 +01:00
doc add @path attribute for spice/verilog/vhdl/tedax backends 2022-11-02 00:47:59 +01:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src code refactoring (update_conn_cues()) 2022-11-07 14:23:57 +01:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating. 2022-11-04 13:35:06 +01:00
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AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions