A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Go to file

stefan schippers aa70d90c46 fix cairo font reference counting		2022-12-25 23:13:59 +01:00
XSchemWin	doc updates (dev info)	2022-12-21 23:07:30 +01:00
doc	doc updates (dev info)	2022-12-21 23:07:30 +01:00
scconfig	added xschem_library/generators directory for future schematic/symbol generator scripts. Handle empty XSCHEM_LIBRARY_PATH (use [pwd]).	2022-12-18 13:03:38 +01:00
src	fix cairo font reference counting	2022-12-25 23:13:59 +01:00
tests	Doc updates (sim_pinnumber), example circuits update	2022-10-17 12:45:48 +02:00
xschem_library	doc updates (dev info)	2022-12-21 23:07:30 +01:00
.gitignore	changed .gitignore for specific xschem files	2020-08-08 23:25:43 +02:00
AUTHORS	update copyright info to 2021; update Product.wxs	2021-09-12 08:32:16 +02:00
Changelog	Update Changelog	2022-07-28 10:31:07 +02:00
INSTALL	populating xschem git repo	2020-08-08 15:47:34 +02:00
LICENSE	update license info	2021-07-27 16:42:54 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile.conf.in	populating xschem git repo	2020-08-08 15:47:34 +02:00
README	update license info	2021-07-27 16:42:54 +02:00
README.md	Update README.md	2020-10-08 00:54:06 +02:00
README_MacOS.md	added notes for MacOS 'Big Sur' builds.	2021-09-26 13:24:51 +02:00
config.h.in	better recognize unknown commands in scheduler.c, re-enabed XCB detection in scconfig (although not used).	2022-12-07 11:32:40 +01:00
configure	populating xschem git repo	2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions