doc updates (dev info)
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@ -654,6 +654,14 @@
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<File Id="fil5FD8BD37B00A8AB4CFA07EFDAE85126F" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\examples\xnor.sym" />
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</Component>
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</Directory>
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<Directory Id="dir0E49847221518A8EA1A21E5E7C2A0013" Name="generators">
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<Component Id="cmpA3A8C99756B5494DF212791423946D83" Guid="{36014B23-7000-4768-9D74-140CFCD1DF1B}">
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<File Id="fil04CAE669A88A44DBB23F914651373D6E" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\generators\gen1.awk" />
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</Component>
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<Component Id="cmpF0846AE0BBACE4805CEC8BB3AEA6C4B6" Guid="{A3909B9E-8464-423D-B6B0-4E1DDBBBCB38}">
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<File Id="filFFB20D471DDD259419E514A8B3810029" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\generators\gmon.out" />
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</Component>
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</Directory>
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<Directory Id="dirC2FFADF72B5C7D98118119748AE42242" Name="gschem_import">
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<Component Id="cmp93CCC992DFDB8670EC1762AF056E9A71" Guid="{DB0D8728-2193-4999-A6D3-7640310FDE36}">
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<File Id="filDDED0159BF7E917F2F3464CF40990F43" KeyPath="yes" Source="$(var.xschemLibrarySrcDir)\gschem_import\24Cxx-1.sym" />
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@ -5652,6 +5660,8 @@
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<ComponentRef Id="cmp30D416247CB7868426C9E8075767CD1A" />
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<ComponentRef Id="cmpB573F1750B3939F980B65D02B78EE0E3" />
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<ComponentRef Id="cmp07A884BAD56D6B1718967173C498C3C3" />
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<ComponentRef Id="cmpA3A8C99756B5494DF212791423946D83" />
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<ComponentRef Id="cmpF0846AE0BBACE4805CEC8BB3AEA6C4B6" />
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<ComponentRef Id="cmp93CCC992DFDB8670EC1762AF056E9A71" />
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<ComponentRef Id="cmp0B11FB04799ACF558B70C4BCB047090B" />
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<ComponentRef Id="cmpE6B72E17713734939AF051305C56B340" />
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@ -147,7 +147,9 @@ p{padding: 15px 30px 10px;}
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<pre class="code">
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C {TECHLIB/PCH} 620 -810 0 0 {name=x5 model=PCHLV w=4 l=0.09 m=1 embed=true}
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[
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G {type=pmos
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v {xschem version=2.9.7 file_version=1.2}
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G {}
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K {type=pmos
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format="@name @pinlist @model w=@w l=@l m=@m"
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verilog_format="@verilog_gate #(@del ) @name ( @@d , @@s , @@g );"
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template=" name=x1 verilog_gate=pmos del=50,50,50 model=PCH w=0.68 l=0.07 m=1 "
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@ -214,7 +216,7 @@ v {xschem version=3.1.0 file_version=1.2
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<h3>GLOBAL SCHEMATIC/SYMBOL PROPERTIES</h3>
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<p>
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Example:<kbd><br>
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G {type=regulator<br>
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K {type=regulator<br>
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format="x@name @pinlist r@symname"<br>
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verilog_format="assign @#2 = @#0 ;"<br>
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tedax_format="footprint @name @footprint<br>
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@ -348,7 +350,8 @@ device="tantalium capacitor"<br>
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</p>
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<h3>EXAMPLE OF A COMPLETE SYMBOL FILE (7805.sym)</h3><br>
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<pre class="code">
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G {type=regulator
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G {}
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K {type=regulator
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format="x@name @pinlist r@symname"
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verilog_format="assign @#2 = @#0 ;"
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tedax_format="footprint @name @footprint
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@ -378,6 +381,7 @@ T {@#2:pinnumber} 47.5 -2.5 0 1 0.12 0.12 {}
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<h3>EXAMPLE OF A COMPLETE SCHEMATIC FILE (pcb_test1.sch)</h3><br>
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<pre class="code">
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G {}
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K {}
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V {}
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S {}
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E {}
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@ -4,6 +4,13 @@ G {}
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K {type=subcircuit
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format="@name @pinlist @symname"
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template="name=x1"
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schematic="tcleval([
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proc hier_config \{f\} \{
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set sch [file rootname $f]
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return $sch.sch
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\}
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hier_config @symname
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])"
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}
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V {}
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S {}
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