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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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schippes 9244b33495 When setting Simulation->LVS netlist, use "lvs_format" attribute for netlisting if this attribute is existing, otherwise keep using "format" 2022-11-24 19:32:16 +01:00
XSchemWin test and get reading schematics from the web on Windows working 2022-11-18 16:06:06 +01:00
doc update documentation for verilogprefix attr. 2022-11-22 18:09:43 +01:00
scconfig monospaced font in code_shown.sym 2022-08-30 15:54:18 +02:00
src When setting Simulation->LVS netlist, use "lvs_format" attribute for netlisting if this attribute is existing, otherwise keep using "format" 2022-11-24 19:32:16 +01:00
tests Doc updates (sim_pinnumber), example circuits update 2022-10-17 12:45:48 +02:00
xschem_library fix regression (not allowing to change text size) 2022-11-23 16:57:21 +01:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS update copyright info to 2021; update Product.wxs 2021-09-12 08:32:16 +02:00
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README_MacOS.md added notes for MacOS 'Big Sur' builds. 2021-09-26 13:24:51 +02:00
config.h.in remove all xrender and all xcb code, remove detection as well. Fix a couple of potentially uninitialized variables 2022-01-19 00:49:46 +01:00
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README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions