Stefan Schippers ec6ad39acc synchronize command sending to gaw with gaw replies so at the end the tcp channel is closed gracefully (avoid port in use error messages). Timeout whatchdog is set to prevent forever waits/deadlocks.		2020-11-07 21:07:16 +01:00
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binto7seg	populating xschem git repo	2020-08-08 15:47:34 +02:00
devices	added res_ac.sym	2020-11-06 19:43:26 +01:00
examples	synchronize command sending to gaw with gaw replies so at the end the tcp channel is closed gracefully (avoid port in use error messages). Timeout whatchdog is set to prevent forever waits/deadlocks.	2020-11-07 21:07:16 +01:00
gschem_import	populating xschem git repo	2020-08-08 15:47:34 +02:00
logic	cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator)	2020-10-13 02:52:37 +02:00
ngspice	get_tok_value: even if called with "with_quotes=2" do not skip unescaped backslashes that are outside "quotes". Added dynamic netlisting test circuit in examples	2020-10-23 23:17:55 +02:00
pcb	fix once again an issue when working in symlinked directories and giving a relative .sch file path on cmdline; clean up print_spice_element(). JL to check if tclgetvar("env(PWD)") works on windows (xinit.c:1435)	2020-10-13 01:07:28 +02:00
rom8k	some clarifications of steps to be taken to simulate example rom8k circuit	2020-10-08 23:24:27 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00