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Stefan Schippers 60791062ac added -b/--batch cmd option (__unix__ only) to detach xschem completely from console
2020-08-31 21:24:03 +02:00
doc
added -b/--batch cmd option (__unix__ only) to detach xschem completely from console
2020-08-31 21:24:03 +02:00
scconfig
removed unused files
2020-08-24 10:01:41 +02:00
src
added -b/--batch cmd option (__unix__ only) to detach xschem completely from console
2020-08-31 21:24:03 +02:00
tests
Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port.
2020-08-10 23:43:20 +02:00
xschem_library
doc updates for text hcenter and vcenter attrs
2020-08-25 02:10:15 +02:00
XSchemWin
Joanne fixes: in print_vhdl_primitive, set variable, format, from "vhdl_format" with get_tok_value before checking if its NULL, more work on windows port.
2020-08-10 23:43:20 +02:00
.gitignore
changed .gitignore for specific xschem files
2020-08-08 23:25:43 +02:00
AUTHORS
populating xschem git repo
2020-08-08 15:47:34 +02:00
Changelog
svg and pdf exports use custom layer colors as set in ~/.xschem/colors file if any.
2020-08-30 12:01:48 +02:00
config.h.in
populating xschem git repo
2020-08-08 15:47:34 +02:00
configure
populating xschem git repo
2020-08-08 15:47:34 +02:00
COPYING
populating xschem git repo
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INSTALL
populating xschem git repo
2020-08-08 15:47:34 +02:00
LICENSE
added LICENSE
2020-08-09 09:12:07 +02:00
Makefile
populating xschem git repo
2020-08-08 15:47:34 +02:00
Makefile.conf.in
populating xschem git repo
2020-08-08 15:47:34 +02:00
README
populating xschem git repo
2020-08-08 15:47:34 +02:00
README.md
Add manual link
2020-08-08 16:04:20 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse. Manual and instructions: http://repo.hu/projects/xschem/xschem_man/xschem_man.html

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Description
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Readme GPL-2.0
62 MiB
Languages
C 72.7%
Tcl 16.3%
Awk 8.2%
Yacc 0.8%
Scheme 0.5%
Other 1.4%